Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 78.
v. lappuse
... simulation. Wayne Wolf (wolf@princeton.edu) is Professor of Electrical Engineering at Princeton University. Before joining Princeton, he was with AT&T Bell Laboratories, Murray Hill, New Jersey. He received the B.S., M.S., and Ph.D ...
... simulation. Wayne Wolf (wolf@princeton.edu) is Professor of Electrical Engineering at Princeton University. Before joining Princeton, he was with AT&T Bell Laboratories, Murray Hill, New Jersey. He received the B.S., M.S., and Ph.D ...
xiv. lappuse
... Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7.1 Gray-Box Model 329 11.7.2 Scenario Selection 329 11.7.3 Reference Cases for Comparison 331 11.7.4 Discussion of All Results 332 11.8 ...
... Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7.1 Gray-Box Model 329 11.7.2 Scenario Selection 329 11.7.3 Reference Cases for Comparison 331 11.7.4 Discussion of All Results 332 11.8 ...
xvi. lappuse
... Simulation Model Generation 382 13.5 Component-Based Design of a VDSL Application 385 13.5.1 The VDSL Modem Architecture Specification 385 Virtual Architecture Specification 387 13.5.2 13.5.3 13.5.4 13.6 Resulting MPSoC Architecture 388 ...
... Simulation Model Generation 382 13.5 Component-Based Design of a VDSL Application 385 13.5.1 The VDSL Modem Architecture Specification 385 Virtual Architecture Specification 387 13.5.2 13.5.3 13.5.4 13.6 Resulting MPSoC Architecture 388 ...
xvii. lappuse
... Simulation Foundation 454 15.4.3 Description of Layered Simulation 455 15.5 Conclusions 462 16 Metropolis: A Design Environment for Heterogeneous Systems 465 Felice Balarin, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alessandro ...
... Simulation Foundation 454 15.4.3 Description of Layered Simulation 455 15.5 Conclusions 462 16 Metropolis: A Design Environment for Heterogeneous Systems 465 Felice Balarin, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alessandro ...
59. lappuse
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa