Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 68.
24. lappuse
... shown in Figure 2-4 [4]. Multiple supply voltages can be used very effectively in MPSoCs since they contain multiple processors of different types with different performance requirements (e.g., as in Fig. 2-2: an MPSoC will contain high ...
... shown in Figure 2-4 [4]. Multiple supply voltages can be used very effectively in MPSoCs since they contain multiple processors of different types with different performance requirements (e.g., as in Fig. 2-2: an MPSoC will contain high ...
26. lappuse
... shown in Figure 2-3. Since increasing the threshold voltage, VT, decreases subthreshold leakage current (exponentially), adjusting VT is one such technique. As shown in Figure 2-5, a 90-mV reduction in VT increases leakage by an order ...
... shown in Figure 2-3. Since increasing the threshold voltage, VT, decreases subthreshold leakage current (exponentially), adjusting VT is one such technique. As shown in Figure 2-5, a 90-mV reduction in VT increases leakage by an order ...
35. lappuse
... shown in Figure 2-10. Data from the source module are encoded, transmitted on the bus, and decoded at the destination. A practical instance of this configuration is the address bus for the processor/memory system. If the bus has very ...
... shown in Figure 2-10. Data from the source module are encoded, transmitted on the bus, and decoded at the destination. A practical instance of this configuration is the address bus for the processor/memory system. If the bus has very ...
46. lappuse
... shown in Figure 2-11, design tradeoffs Time PR TR AT2 PT3 1/Reliability Power Area 2-11 47 have changed over the years from a focus on. Evolving design tradeoffs. T, time; R, reliability; A, area; P, power; PT, product of power and time ...
... shown in Figure 2-11, design tradeoffs Time PR TR AT2 PT3 1/Reliability Power Area 2-11 47 have changed over the years from a focus on. Evolving design tradeoffs. T, time; R, reliability; A, area; P, power; PT, product of power and time ...
54. lappuse
... shown in Figure 3-2. In this approach, the channel is abstracted by a transfer function FC(f) in the frequency domain. The transmitter and the receiver should equalize the transfer function by jointly implementing its inverse: FT(f)◊FR ...
... shown in Figure 3-2. In this approach, the channel is abstracted by a transfer function FC(f) in the frequency domain. The transmitter and the receiver should equalize the transfer function by jointly implementing its inverse: FT(f)◊FR ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa