Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 90.
xi. lappuse
... Shared Resources 171 6.4.1 Resource Sharing Principle and Impact 171 6.4.2 Static Execution Order Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global ...
... Shared Resources 171 6.4.1 Resource Sharing Principle and Impact 171 6.4.2 Static Execution Order Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global ...
6. lappuse
... shared-memory multiprocessor [2]—a pool of processors and a pool of memory are connected by an interconnection network. Each is generally regularly structured, and the programmer is given a regular programming model. A shared-memory ...
... shared-memory multiprocessor [2]—a pool of processors and a pool of memory are connected by an interconnection network. Each is generally regularly structured, and the programmer is given a regular programming model. A shared-memory ...
13. lappuse
... shared data transfer. This fixed memory architecture, besides the limited number and types of the incorporated CPU cores, reduces the application field of the proposed platform. However, the diversity of the hardware components included ...
... shared data transfer. This fixed memory architecture, besides the limited number and types of the incorporated CPU cores, reduces the application field of the proposed platform. However, the diversity of the hardware components included ...
14. lappuse
... shared-memory programming and message-passing programming. OpenMP and message-passing interface (MPI) are examples, respectively. When using conventional parallel programming models for SoC, we face conventional issues in parallel ...
... shared-memory programming and message-passing programming. OpenMP and message-passing interface (MPI) are examples, respectively. When using conventional parallel programming models for SoC, we face conventional issues in parallel ...
17. lappuse
... shared memory and distributed memory. Shared-memory architecture usually requires local caches and cache coherency protocols to prevent the performance bottlenecks. Distributed memory can be classified into several levels according to ...
... shared memory and distributed memory. Shared-memory architecture usually requires local caches and cache coherency protocols to prevent the performance bottlenecks. Distributed memory can be classified into several levels according to ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa