Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 82.
xi. lappuse
... Scheduling 172 Time-Driven Scheduling 173 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 Global Performance Analysis 179 Conclusions 185 7 Design of Communication Architectures for High- Performance and Energy ...
... Scheduling 172 Time-Driven Scheduling 173 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 Global Performance Analysis 179 Conclusions 185 7 Design of Communication Architectures for High- Performance and Energy ...
xi. lappuse
... Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication Architectures for HighPerformance ...
... Scheduling 172 6.4.3 Time-Driven Scheduling 173 6.4.4 Priority-Driven Scheduling 176 6.4.5 Resource Sharing-Summary 178 6.5 Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication Architectures for HighPerformance ...
xiii. lappuse
... Scheduling 288 Basic System Model 290 Uniprocessor Systems 292 10.4.1 Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 Resource Allocation Model 302 249 251 283 xiii xiv 10.5 ...
... Scheduling 288 Basic System Model 290 Uniprocessor Systems 292 10.4.1 Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 Resource Allocation Model 302 249 251 283 xiii xiv 10.5 ...
xiv. lappuse
... Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7.1 Gray-Box Model 329 11.7.2 Scenario ...
... Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7.1 Gray-Box Model 329 11.7.2 Scenario ...
10. lappuse
... scheduling mechanisms for tasks, but they also abstract the process. The detailed behavior of a task—how it accesses memory, its flow of control—can influence its execution time and therefore the system schedule that is managed by the ...
... scheduling mechanisms for tasks, but they also abstract the process. The detailed behavior of a task—how it accesses memory, its flow of control—can influence its execution time and therefore the system schedule that is managed by the ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa