Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 81.
xii. lappuse
... Platform 238 8.5.1 Architectural Modeling 240 8.5.2 Mapping and Communication Refinement 241 Results 243 8.6.1 Communication Refinement 245 8.6.2 FPGA Alternatives 246 Conclusions 248 PART II 9 SOFTWARE Memory Systems and Compiler ...
... Platform 238 8.5.1 Architectural Modeling 240 8.5.2 Mapping and Communication Refinement 241 Results 243 8.6.1 Communication Refinement 245 8.6.2 FPGA Alternatives 246 Conclusions 248 PART II 9 SOFTWARE Memory Systems and Compiler ...
xiii. lappuse
... Platform Architecture 286 10.2.2 Tasks 286 10.2.3 Basics of Scheduling 288 Basic System Model 290 Uniprocessor Systems 292 10.4.1 Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 ...
... Platform Architecture 286 10.2.2 Tasks 286 10.2.3 Basics of Scheduling 288 Basic System Model 290 Uniprocessor Systems 292 10.4.1 Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 ...
xiv. lappuse
... Platform Based Design 314 11.3 Related Work 315 11.4 Target Platform Architecture and Model 319 11.5 Task Concurrency Management 320 11.5.1 Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to ...
... Platform Based Design 314 11.3 Related Work 315 11.4 Target Platform Architecture and Model 319 11.5 Task Concurrency Management 320 11.5.1 Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to ...
xvi. lappuse
... Platform-Based Design 413 The Ever Critical Communication Bus Structures 416 14.7.1 PNX-8500 Structure 417 Design for Testability 421 Application-Driven Architecture Design 423 14.9.1 Application Characterization 423 14.9.2 ...
... Platform-Based Design 413 The Ever Critical Communication Bus Structures 416 14.7.1 PNX-8500 Structure 417 Design for Testability 421 Application-Driven Architecture Design 423 14.9.1 Application Characterization 423 14.9.2 ...
xviii. lappuse
... 484 16.4.2 Architectural Platform 489 16.4.3 Mapping Strategy 492 Conclusions 495 Glossary 497 References 513 Contributor Biographies 557 Subject Index 567 Preface This book had its origins in the Multiprocessor System-on-Chip Contents.
... 484 16.4.2 Architectural Platform 489 16.4.3 Mapping Strategy 492 Conclusions 495 Glossary 497 References 513 Contributor Biographies 557 Subject Index 567 Preface This book had its origins in the Multiprocessor System-on-Chip Contents.
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa