Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 92.
ix. lappuse
... Performance Processors: ACommon Foundation 82 4.3 Pipelining Techniques 85 4.3.1 Bypasses 86 4.3.2 Branch Prediction ... Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non-Determinism Without ...
... Performance Processors: ACommon Foundation 82 4.3 Pipelining Techniques 85 4.3.1 Bypasses 86 4.3.2 Branch Prediction ... Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non-Determinism Without ...
x. lappuse
... Performance 136 5.3.7 Extensibility and Energy Efficiency 142 5.4 Toward Multiple-Processor SoCs 142 5.4.1 Modeling ... Performance Modeling and Analysis 153 Rolf Ernst 6.1 Introduction 153 6.1.1 Complex Heterogeneous Architectures 153 ...
... Performance 136 5.3.7 Extensibility and Energy Efficiency 142 5.4 Toward Multiple-Processor SoCs 142 5.4.1 Modeling ... Performance Modeling and Analysis 153 Rolf Ernst 6.1 Introduction 153 6.1.1 Complex Heterogeneous Architectures 153 ...
2. lappuse
... performance I/O applications require a separate analog interface chip that serves as a companion to a digital SoC, most of an SoC is digital because that is the only way to build such complex functions reliably. The system may contain ...
... performance I/O applications require a separate analog interface chip that serves as a companion to a digital SoC, most of an SoC is digital because that is the only way to build such complex functions reliably. The system may contain ...
4. lappuse
... performance? Because most of the applications for which SoCs are used have precise performance requirements. In traditional interactive computing, we care about speed but not about deadlines. Control systems, protocols, and most real ...
... performance? Because most of the applications for which SoCs are used have precise performance requirements. In traditional interactive computing, we care about speed but not about deadlines. Control systems, protocols, and most real ...
6. lappuse
... performance computation. Why not use a single platform for all applications? Why not build SoCs like field programmable gate arrays (FPGAs), in which a single architecture is built in a variety of sizes? And why use a multiprocessor ...
... performance computation. Why not use a single platform for all applications? Why not build SoCs like field programmable gate arrays (FPGAs), in which a single architecture is built in a variety of sizes? And why use a multiprocessor ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa