Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 43.
10. lappuse
... packet networks to interconnect the processors in the SoC. Although a great deal is known about networks, traditional network design assumes relatively little about the characteristics of the traffic on the network. SoC applications can ...
... packet networks to interconnect the processors in the SoC. Although a great deal is known about networks, traditional network design assumes relatively little about the characteristics of the traffic on the network. SoC applications can ...
10. lappuse
... packet networks to interconnect the processors in the SoC. Although a great deal is known about networks, traditional network design assumes relatively little about the characteristics of the traffic on the network. SoC applications can ...
... packet networks to interconnect the processors in the SoC. Although a great deal is known about networks, traditional network design assumes relatively little about the characteristics of the traffic on the network. SoC applications can ...
41. lappuse
... packet. When communi- cation flow between network nodes is extremely persistent and stationary, circuit- switched schemes are likely to be preferable, whereas packet switched schemes should be more energy-efficient for irregular and non ...
... packet. When communi- cation flow between network nodes is extremely persistent and stationary, circuit- switched schemes are likely to be preferable, whereas packet switched schemes should be more energy-efficient for irregular and non ...
42. lappuse
... packets in the network, (2) the energy consumed by each packet on one hop, and (3) the number of hops each packet travels. Different packetization schemes will have different impact on these factors and, consequently, affect the network ...
... packets in the network, (2) the energy consumed by each packet on one hop, and (3) the number of hops each packet travels. Different packetization schemes will have different impact on these factors and, consequently, affect the network ...
43. lappuse
... packet, thus mini- mizing control bits overhead, although this would prevent us from stopping the propagation of corrupted flits, as routing decisions would be taken in advance with respect to data integrity checking. In fact, control ...
... packet, thus mini- mizing control bits overhead, although this would prevent us from stopping the propagation of corrupted flits, as routing decisions would be taken in advance with respect to data integrity checking. In fact, control ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa