Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 83.
xiii. lappuse
... Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 Resource Allocation Model 302 xiii xiv 11 Multiprocessor Systems 303 10.5 10.5.1 10.6 Multiprocessing Anomalies Contents.
... Link Model 292 10.4.2 Task Model 293 10.4.3 Scheduler Model 296 10.4.4 Synchronization Model 300 10.4.5 Resource Allocation Model 302 xiii xiv 11 Multiprocessor Systems 303 10.5 10.5.1 10.6 Multiprocessing Anomalies Contents.
xiv. lappuse
Ahmed Jerraya, Wayne Wolf. xiv 11 Multiprocessor Systems 303 10.5 10.5.1 10.6 Multiprocessing Anomalies 306 10.5.2 Interprocessor Communication 308 10.5.3 Multiprocessor Example 309 Summary 311 Cost-Efficient Mapping of Dynamic ...
Ahmed Jerraya, Wayne Wolf. xiv 11 Multiprocessor Systems 303 10.5 10.5.1 10.6 Multiprocessing Anomalies 306 10.5.2 Interprocessor Communication 308 10.5.3 Multiprocessor Example 309 Summary 311 Cost-Efficient Mapping of Dynamic ...
xiv. lappuse
Ahmed Jerraya, Wayne Wolf. xiv 10.5 Multiprocessor Systems 303 10.5.1 Multiprocessing Anomalies 306 10.5.2 Interprocessor Communication 308 10.5.3 Multiprocessor Example 309 10.6 Summary 311 11 Cost-Efficient Mapping of Dynamic ...
Ahmed Jerraya, Wayne Wolf. xiv 10.5 Multiprocessor Systems 303 10.5.1 Multiprocessing Anomalies 306 10.5.2 Interprocessor Communication 308 10.5.3 Multiprocessor Example 309 10.6 Summary 311 11 Cost-Efficient Mapping of Dynamic ...
xvii. lappuse
... Multiprocessors 452 15.4.2 A New Simulation Foundation 454 15.4.3 Description of Layered Simulation 455 15.5 Conclusions 462 16 Metropolis: A Design Environment for Heterogeneous Systems 465 Felice Balarin, Harry Hsieh, Luciano Lavagno ...
... Multiprocessors 452 15.4.2 A New Simulation Foundation 454 15.4.3 Description of Layered Simulation 455 15.5 Conclusions 462 16 Metropolis: A Design Environment for Heterogeneous Systems 465 Felice Balarin, Harry Hsieh, Luciano Lavagno ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa