Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 86.
ix. lappuse
... Multiple-Instruction Issue, and Hardware Multithreading 93 4.4 Survey of General-purpose 32-bit Embedded Microprocessors 96 4.4.1 ARM 98 4.4.2 High-end Embedded MPUs 103 4.4.3 Ubicom IP3023: Deterministic High Performance via ...
... Multiple-Instruction Issue, and Hardware Multithreading 93 4.4 Survey of General-purpose 32-bit Embedded Microprocessors 96 4.4.1 ARM 98 4.4.2 High-end Embedded MPUs 103 4.4.3 Ubicom IP3023: Deterministic High Performance via ...
x. lappuse
... Multiple-Processor SoCs 142 5.4.1 Modeling Systems with Multiple Processors 144 5.4.2 Developing an XTMP Model 144 5.5 Processors and Disruptive Technology 147 5.6 Conclusions 149 6 MPSoC Performance Modeling and Analysis 153 Rolf Ernst ...
... Multiple-Processor SoCs 142 5.4.1 Modeling Systems with Multiple Processors 144 5.4.2 Developing an XTMP Model 144 5.5 Processors and Disruptive Technology 147 5.6 Conclusions 149 6 MPSoC Performance Modeling and Analysis 153 Rolf Ernst ...
2. lappuse
... multiple instruction-set processors (CPUs). In practice, most SoCs are MPSoCs because it is too difficult to design a complex system-on-chip without making use of 3 Audio out Audio decode On-chip memory Off-chip memory Error 1 The What ...
... multiple instruction-set processors (CPUs). In practice, most SoCs are MPSoCs because it is too difficult to design a complex system-on-chip without making use of 3 Audio out Audio decode On-chip memory Off-chip memory Error 1 The What ...
8. lappuse
... multiple processors; for example, they may decompose a matrix in parallel using several CPUs. However, the task-level parallelism that embedded computing applications display is inherently heterogeneous. In the MPEG block 1 The What ...
... multiple processors; for example, they may decompose a matrix in parallel using several CPUs. However, the task-level parallelism that embedded computing applications display is inherently heterogeneous. In the MPEG block 1 The What ...
11. lappuse
... multiple processor cores and associated peripherals—a higher abstraction level is needed on the hardware side. When designers use RTL abstractions, they can produce, on average, the equivalent of4 to 10 gates per line of RTL code. 12 ...
... multiple processor cores and associated peripherals—a higher abstraction level is needed on the hardware side. When designers use RTL abstractions, they can produce, on average, the equivalent of4 to 10 gates per line of RTL code. 12 ...
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa