Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 93.
xiii. lappuse
... Memory Architectures 252 9.2.1 Types of Architectures 254 9.2.2 Customization of Memory Architectures 261 9.2.3 Reconfigurability and Challenges 267 Compiler Support 269 9.3.1 Problems 269 9.3.2 Solutions 271 Conclusions 281 ...
... Memory Architectures 252 9.2.1 Types of Architectures 254 9.2.2 Customization of Memory Architectures 261 9.2.3 Reconfigurability and Challenges 267 Compiler Support 269 9.3.1 Problems 269 9.3.2 Solutions 271 Conclusions 281 ...
2. lappuse
... memory, instruction-set processors (central processing units [CPUs]), specialized logic, busses, and other digital ... memory Off-chip memory Error 1 The What, Why, and How of MPSoCs.
... memory, instruction-set processors (central processing units [CPUs]), specialized logic, busses, and other digital ... memory Off-chip memory Error 1 The What, Why, and How of MPSoCs.
5. lappuse
... memory model for programmers. Although these regular, simple architectures are simple for programmers, they are often more expensive and less energy efficient than heterogeneous ... Memory Memory ... 1.3 Why MPSoCs? 1.3 Why MPSoCs?
... memory model for programmers. Although these regular, simple architectures are simple for programmers, they are often more expensive and less energy efficient than heterogeneous ... Memory Memory ... 1.3 Why MPSoCs? 1.3 Why MPSoCs?
6. lappuse
... Memory ... Memory 1-3 FIGURE A generic shared-memory multiprocessor. may also be heterogeneous. MPSoCs often require large amounts of memory. The device may have embedded memory on-chip as well as relying on off-chip commodity memory ...
... Memory ... Memory 1-3 FIGURE A generic shared-memory multiprocessor. may also be heterogeneous. MPSoCs often require large amounts of memory. The device may have embedded memory on-chip as well as relying on off-chip commodity memory ...
8. lappuse
... memory, but memory incurs both area and energy consumption costs. Making sure that the processor can produce results at predictable times generally requires careful design of all the aspects of the hardware: instruction set, memory ...
... memory, but memory incurs both area and energy consumption costs. Making sure that the processor can produce results at predictable times generally requires careful design of all the aspects of the hardware: instruction set, memory ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa