Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 80.
x. lappuse
... Integration 120 5.2.2 The Limitations of General-Purpose Processors 120 5.2.3 DSP as Application-Specific Processor 122 5.3 Extensible Processors as an Alternative to RTL 122 5.3.1 The Origins of Configurable Processors 123 5.3.2 ...
... Integration 120 5.2.2 The Limitations of General-Purpose Processors 120 5.2.3 DSP as Application-Specific Processor 122 5.3 Extensible Processors as an Alternative to RTL 122 5.3.1 The Origins of Configurable Processors 123 5.3.2 ...
1. lappuse
... integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors, and the International Technology Roadmap for Semiconductors predicts that chips with a billion transistors are within reach. Harnessing ...
... integration (VLSI) technology. A single integrated circuit can contain over 100 million transistors, and the International Technology Roadmap for Semiconductors predicts that chips with a billion transistors are within reach. Harnessing ...
10. lappuse
... integrated circuits (ASICs) in many markets. FPGA fabrics are also starting to be integrated into SoCs. The FPGA logic can be used for custom logic that could not be designed before manufacturing. This approach is a good complement to ...
... integrated circuits (ASICs) in many markets. FPGA fabrics are also starting to be integrated into SoCs. The FPGA logic can be used for custom logic that could not be designed before manufacturing. This approach is a good complement to ...
11. lappuse
... integrated into these chips. But, more important, MPSoCs that are organized into networks of chips do not have total control over the system. When designing a single chip, the design team has total control over what goes onto the chip ...
... integrated into these chips. But, more important, MPSoCs that are organized into networks of chips do not have total control over the system. When designing a single chip, the design team has total control over what goes onto the chip ...
12. lappuse
... integration into a system also presents a variety of challenges. A complete design flow for MPSoCs includes refinement processes that require multiple competences and tools because of the complexity and diversity of the current ...
... integration into a system also presents a variety of challenges. A complete design flow for MPSoCs includes refinement processes that require multiple competences and tools because of the complexity and diversity of the current ...
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa