Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 64.
2. lappuse
... input/output (I/O). Although some high-performance I/O applications require a separate analog interface chip that serves as a companion to a digital SoC, most of an SoC is digital because that is the only way to build such complex ...
... input/output (I/O). Although some high-performance I/O applications require a separate analog interface chip that serves as a companion to a digital SoC, most of an SoC is digital because that is the only way to build such complex ...
3. lappuse
... inputs from the laser pickup must be decoded both to be sure that the laser is on track and to read the data from the disc. A small number of analog outputs controls the lens and sled to keep the laser on the data track, which is ...
... inputs from the laser pickup must be decoded both to be sure that the laser is on track and to read the data from the disc. A small number of analog outputs controls the lens and sled to keep the laser on the data track, which is ...
9. lappuse
... input and output devices could be implemented in a generic fashion given enough transistors; to some extent, this has been done for FPGA I/O pads. But given the variety of physical interfaces that exist, it can be difficult to create ...
... input and output devices could be implemented in a generic fashion given enough transistors; to some extent, this has been done for FPGA I/O pads. But given the variety of physical interfaces that exist, it can be difficult to create ...
24. lappuse
... Input control Variable VT. 2.2.1. time mechanisms—by either the hardware (e.g., in the case of clock gating) or the system software (e.g., in the case of dynamic voltage scaling [DVS]). In the case of software control, the cost of ...
... Input control Variable VT. 2.2.1. time mechanisms—by either the hardware (e.g., in the case of clock gating) or the system software (e.g., in the case of dynamic voltage scaling [DVS]). In the case of software control, the cost of ...
34. lappuse
... input streams was implicitly assumed to be unitary. In other words, no modulation and encoding were applied to the binary data before sending it on the bus. Low-energy communication techniques remove this implicit assumption, by ...
... input streams was implicitly assumed to be unitary. In other words, no modulation and encoding were applied to the binary data before sending it on the bus. Low-energy communication techniques remove this implicit assumption, by ...
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa