Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 87.
7. lappuse
... implementation on the SoC. It is the job of software or hardware design tools to massage the decomposition based on implementation costs. But having the original parallelism explicitly specified makes it much easier to repartition the ...
... implementation on the SoC. It is the job of software or hardware design tools to massage the decomposition based on implementation costs. But having the original parallelism explicitly specified makes it much easier to repartition the ...
13. lappuse
... implementation of wireless applications. The two processing units consist of an ARM9 core (@ 150MHz) and a C55x DSP core (@ 200MHz). Both of them have a 16-Kb I-cache, an 8-Kb D-cache, and a two-way set 14 1.7 associative global cache ...
... implementation of wireless applications. The two processing units consist of an ARM9 core (@ 150MHz) and a C55x DSP core (@ 200MHz). Both of them have a 16-Kb I-cache, an 8-Kb D-cache, and a two-way set 14 1.7 associative global cache ...
37. lappuse
... implementation overhead (in terms of power) is small. Extensions to the bus invert encoding approach include the use ... implemented using additional bus lines, there are other options. In particular, it is possible to communicate with ...
... implementation overhead (in terms of power) is small. Extensions to the bus invert encoding approach include the use ... implemented using additional bus lines, there are other options. In particular, it is possible to communicate with ...
40. lappuse
... implementation. The energy efficiency of a code is tightly related to its error recovery technique, namely, error correction or retransmission of corrupted data. This issue resembles the tradeoff investigation between forward error ...
... implementation. The energy efficiency of a code is tightly related to its error recovery technique, namely, error correction or retransmission of corrupted data. This issue resembles the tradeoff investigation between forward error ...
53. lappuse
... implementation of the communication channels. The technologies under consideration will exceed 10 wiring levels. Most likely, global wires will be routed on the top metal layers provided by the technology. The pitch (i.e., width plus ...
... implementation of the communication channels. The technologies under consideration will exceed 10 wiring levels. Most likely, global wires will be routed on the top metal layers provided by the technology. The pitch (i.e., width plus ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa