Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 69.
ix. lappuse
Ahmed Jerraya, Wayne Wolf. 3.2 Signal Transmission on Chip 52 3.2.1 Global Wiring and Signaling 53 3.2.2 Signal Integrity 55 Micronetwork Architecture and Control 3.3 3.3.1 57 Interconnection Network Architectures 58 3.3.2 Micronetwork ...
Ahmed Jerraya, Wayne Wolf. 3.2 Signal Transmission on Chip 52 3.2.1 Global Wiring and Signaling 53 3.2.2 Signal Integrity 55 Micronetwork Architecture and Control 3.3 3.3.1 57 Interconnection Network Architectures 58 3.3.2 Micronetwork ...
ix. lappuse
... Global Wiring and Signaling 53 3.2.2 Signal Integrity 55 3.3 Micronetwork Architecture and Control 57 3.3.1 Interconnection Network Architectures 58 3.3.2 Micronetwork Control 63 3.4 Software Layers 73 3.4.1 Programming Model 73 3.4.2 ...
... Global Wiring and Signaling 53 3.2.2 Signal Integrity 55 3.3 Micronetwork Architecture and Control 57 3.3.1 Interconnection Network Architectures 58 3.3.2 Micronetwork Control 63 3.4 Software Layers 73 3.4.1 Programming Model 73 3.4.2 ...
xi. lappuse
... Global Performance Analysis 179 Conclusions 185 7 Design of Communication Architectures for High- Performance and Energy-Efficient Systems-on-Chips 187 Sujit Dey, Kanishka Lahiri, and Anand Raghunathan Introduction 187 On-Chip ...
... Global Performance Analysis 179 Conclusions 185 7 Design of Communication Architectures for High- Performance and Energy-Efficient Systems-on-Chips 187 Sujit Dey, Kanishka Lahiri, and Anand Raghunathan Introduction 187 On-Chip ...
xi. lappuse
... Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication Architectures for HighPerformance and Energy-Efficient Systems-on-Chips 187 Sujit Dey, Kanishka Lahiri, and Anand Raghunathan 7.1 Introduction 187 7.2 On-Chip ...
... Global Performance Analysis 179 6.6 Conclusions 185 7 Design of Communication Architectures for HighPerformance and Energy-Efficient Systems-on-Chips 187 Sujit Dey, Kanishka Lahiri, and Anand Raghunathan 7.1 Introduction 187 7.2 On-Chip ...
xiv. lappuse
... Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7 ...
... Global TCM Methodology 321 11.5.2 Two-Phase Scheduling Stage 321 11.5.3 Scenarios to Characterize Data-Dependent TFs 324 11.5.4 Platform Simulation Environment 326 11.6 3D Rendering QoS Application 327 11.7 Experimental Results 329 11.7 ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa