Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 54.
ix. lappuse
... General-purpose 32-bit Embedded Microprocessors 96 4.4.1 ARM 98 4.4.2 High-end Embedded MPUs 103 4.4.3 Ubicom IP3023: Deterministic High Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non ...
... General-purpose 32-bit Embedded Microprocessors 96 4.4.1 ARM 98 4.4.2 High-end Embedded MPUs 103 4.4.3 Ubicom IP3023: Deterministic High Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non ...
x. lappuse
... General-Purpose Processors 120 5.2.3 DSP as Application-Specific Processor 122 5.3 Extensible Processors as an ... Objectives 159 6.1.5 Structuring Performance Analysis 160 xi 6.2 Architecture Component Performance Modeling and Analysis ...
... General-Purpose Processors 120 5.2.3 DSP as Application-Specific Processor 122 5.3 Extensible Processors as an ... Objectives 159 6.1.5 Structuring Performance Analysis 160 xi 6.2 Architecture Component Performance Modeling and Analysis ...
2. lappuse
... general-purpose computer architectures either because a general-purpose machine is not cost-effective or because it would simply not provide the necessary performance. Consumer devices must sell for extremely low prices. Today, digital ...
... general-purpose computer architectures either because a general-purpose machine is not cost-effective or because it would simply not provide the necessary performance. Consumer devices must sell for extremely low prices. Today, digital ...
4. lappuse
... general-purpose CPU that executes the millions of instructions per second (MIPS) instruction set and two vector processing units, VPU0 and VPU1. The two vector processing units have different internal architectures. The chip contains ...
... general-purpose CPU that executes the millions of instructions per second (MIPS) instruction set and two vector processing units, VPU0 and VPU1. The two vector processing units have different internal architectures. The chip contains ...
8. lappuse
... general-purpose computing to provide performance in an easy programming model make the system's performance less predictable. Snooping caching, for example, dynamically manages cache coherency but at the cost of less predictable delays ...
... general-purpose computing to provide performance in an easy programming model make the system's performance less predictable. Snooping caching, for example, dynamically manages cache coherency but at the cost of less predictable delays ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa