Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 85.
xiv. lappuse
... Example 309 Summary 311 Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems ... Examples 339 324 313 337 12.3 12.4 12.2.1 12.2.2 12.2.3 Instruction Scheduling 341 Energy Efficiency Contents.
... Example 309 Summary 311 Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems ... Examples 339 324 313 337 12.3 12.4 12.2.1 12.2.2 12.2.3 Instruction Scheduling 341 Energy Efficiency Contents.
xiv. lappuse
... Example 309 10.6 Summary 311 11 Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia ... Examples 339 xv 12.2.1 Instruction Scheduling 341 12.2.2 Energy Efficiency 343 12.2.3 Contents.
... Example 309 10.6 Summary 311 11 Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia ... Examples 339 xv 12.2.1 Instruction Scheduling 341 12.2.2 Energy Efficiency 343 12.2.3 Contents.
6. lappuse
... example of a regular architecture designed for high-performance computation. Why not use a single platform for all applications? Why not build SoCs like field programmable gate arrays (FPGAs), in which a single architecture is built in ...
... example of a regular architecture designed for high-performance computation. Why not use a single platform for all applications? Why not build SoCs like field programmable gate arrays (FPGAs), in which a single architecture is built in ...
7. lappuse
... example, Figure 1-4 shows the block diagram for MPEG-2 encoding [4]. Video encoding requires several operations to run concurrently: motion estimation, discrete cosine transform (DCT), and Huffman coding, among others. Video frames ...
... example, Figure 1-4 shows the block diagram for MPEG-2 encoding [4]. Video encoding requires several operations to run concurrently: motion estimation, discrete cosine transform (DCT), and Huffman coding, among others. Video frames ...
8. lappuse
... example—but they also require that the results be available at a predictable rate. Rate variations can often be solved by adding buffer memory, but memory incurs both area and energy consumption costs. Making sure that the processor can ...
... example—but they also require that the results be available at a predictable rate. Rate variations can often be solved by adding buffer memory, but memory incurs both area and energy consumption costs. Making sure that the processor can ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa