Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 39.
2. lappuse
... decoding and user interface functions. ✦ Television production equipment uses systems-on-chips to encode video ... decoder and control system that playing DVDs requires. At the high end, general-purpose machines simply can't keep ...
... decoding and user interface functions. ✦ Television production equipment uses systems-on-chips to encode video ... decoder and control system that playing DVDs requires. At the high end, general-purpose machines simply can't keep ...
3. lappuse
... decoded both to be sure that the laser is on track and to read the data from the disc. A small number of analog outputs controls the lens and sled to keep the laser on the data track, which is arranged as a spiral around the disc. Early ...
... decoded both to be sure that the laser is on track and to read the data from the disc. A small number of analog outputs controls the lens and sled to keep the laser on the data track, which is arranged as a spiral around the disc. Early ...
4. lappuse
... decoded into audio data; typically other user functions such as equalization are performed at the same time. MP3 decoding can be performed relatively cheaply, so a relatively unsophisticated CPU is all that is required for this final ...
... decoded into audio data; typically other user functions such as equalization are performed at the same time. MP3 decoding can be performed relatively cheaply, so a relatively unsophisticated CPU is all that is required for this final ...
35. lappuse
... decoders. The complexity and energy cost of encoding and decoding circuits must be taken into account when evaluating any bus-encoding scheme. Several authors have proposed low-transition activity encoding and decoding schemes. To ...
... decoders. The complexity and energy cost of encoding and decoding circuits must be taken into account when evaluating any bus-encoding scheme. Several authors have proposed low-transition activity encoding and decoding schemes. To ...
36. lappuse
... decoding). However, as discussed in the following, this assumption has to be carefully validated whenever a new encoding scheme is proposed. Encoding. for. Random. White. Noise. A few encoding schemes have been studied starting from the ...
... decoding). However, as discussed in the following, this assumption has to be carefully validated whenever a new encoding scheme is proposed. Encoding. for. Random. White. Noise. A few encoding schemes have been studied starting from the ...
Citi izdevumi - Skatīt visu
Bieži izmantoti vārdi un frāzes
abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa