Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 78.
11. lappuse
... cores and associated peripherals — a higher abstrac- tion level is needed on the hardware side . When designers use RTL abstractions , they can produce , on average , the equivalent of 4 to 10 gates per line of RTL code . 11 12 Thus ...
... cores and associated peripherals — a higher abstrac- tion level is needed on the hardware side . When designers use RTL abstractions , they can produce , on average , the equivalent of 4 to 10 gates per line of RTL code . 11 12 Thus ...
13. lappuse
... core ( 32- bit or 64 - bit @ 50 to 300 + MHz ) . It also contains a library of dedicated hardware processing units ... core ( @ 150 MHz ) and a C55x DSP core ( @ 200 MHz ) . Both of them have a 16 - Kb I - cache , an 8 - Kb D - cache ...
... core ( 32- bit or 64 - bit @ 50 to 300 + MHz ) . It also contains a library of dedicated hardware processing units ... core ( @ 150 MHz ) and a C55x DSP core ( @ 200 MHz ) . Both of them have a 16 - Kb I - cache , an 8 - Kb D - cache ...
14. lappuse
... cores). Virtex-II ProTM from Xilinx is a recent FPGA architecture that embeds 0, 1, 2, or 4 PowerPC cores. Each PowerPC core occupies only about 2% of the total die area. The rest of the die area can be used to implement system busses ...
... cores). Virtex-II ProTM from Xilinx is a recent FPGA architecture that embeds 0, 1, 2, or 4 PowerPC cores. Each PowerPC core occupies only about 2% of the total die area. The rest of the die area can be used to implement system busses ...
17. lappuse
... core functionality of the intended application. From the viewpoint of the designer who optimizes the soft- ware performance and cost, the design of an application-specific processor and corresponding compiler is a challenging design ...
... core functionality of the intended application. From the viewpoint of the designer who optimizes the soft- ware performance and cost, the design of an application-specific processor and corresponding compiler is a challenging design ...
23. lappuse
... cores . Section 2.3 focuses on the on - chip memory hierarchy , Section 2.4 on the on - chip communication system , and Section 2.5 on energy - aware software techniques that can be used in MPSoC designs . We close with conclusions ...
... cores . Section 2.3 focuses on the on - chip memory hierarchy , Section 2.4 on the on - chip communication system , and Section 2.5 on energy - aware software techniques that can be used in MPSoC designs . We close with conclusions ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa