Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 81.
5. lappuse
... constraints typically reserved for hardware, such as hard timing constraints and energy consumption. This melding of hardware and software design disciplines is one of the things that makes MPSoC design interesting and challenging. The ...
... constraints typically reserved for hardware, such as hard timing constraints and energy consumption. This melding of hardware and software design disciplines is one of the things that makes MPSoC design interesting and challenging. The ...
8. lappuse
... constraints push SoC designers toward heterogeneous multiprocessors. We can consider these constraints in more detail. Real-time computing is much more than high-performance computing. Many SoC applications require very high performance ...
... constraints push SoC designers toward heterogeneous multiprocessors. We can consider these constraints in more detail. Real-time computing is much more than high-performance computing. Many SoC applications require very high performance ...
11. lappuse
... constraints. System-level modeling is the enabling technology for MPSoC design. Registertransfer level (RTL) models are too time consuming to design and verify when considering multiple processor cores and associated peripherals—a ...
... constraints. System-level modeling is the enabling technology for MPSoC design. Registertransfer level (RTL) models are too time consuming to design and verify when considering multiple processor cores and associated peripherals—a ...
12. lappuse
... constraints and metrics. High-level abstractions make global MPSoC design methodologies possible by hiding precise circuit behavior—notably accurate timing information—from system-level designers and tools. However, MPSoCs are mostly ...
... constraints and metrics. High-level abstractions make global MPSoC design methodologies possible by hiding precise circuit behavior—notably accurate timing information—from system-level designers and tools. However, MPSoCs are mostly ...
16. lappuse
... constraints, the software architecture needs to be designed to minimize its overhead. For instance, instead of using a full-featured OS, the OS needs only to support the functions required by the application software and MPSoC ...
... constraints, the software architecture needs to be designed to minimize its overhead. For instance, instead of using a full-featured OS, the OS needs only to support the functions required by the application software and MPSoC ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa