Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 82.
xii. lappuse
... Architectural Modeling 240 8.5.2 Mapping and Communication Refinement 241 Results 243 8.6.1 Communication Refinement 245 8.6.2 FPGA Alternatives 246 Conclusions 248 PART II 9 SOFTWARE Memory Systems and Compiler Support for Contents.
... Architectural Modeling 240 8.5.2 Mapping and Communication Refinement 241 Results 243 8.6.1 Communication Refinement 245 8.6.2 FPGA Alternatives 246 Conclusions 248 PART II 9 SOFTWARE Memory Systems and Compiler Support for Contents.
xiii. lappuse
... Compiler Support 269 9.3.1 Problems 269 9.3.2 Solutions 271 Conclusions 281 Introduction 283 Basic Concepts and Terminology 286 10.2.1 Platform Architecture 286 10.2.2 Tasks 286 10.2.3 Basics of Scheduling 288 Basic System Model 290 ...
... Compiler Support 269 9.3.1 Problems 269 9.3.2 Solutions 271 Conclusions 281 Introduction 283 Basic Concepts and Terminology 286 10.2.1 Platform Architecture 286 10.2.2 Tasks 286 10.2.3 Basics of Scheduling 288 Basic System Model 290 ...
10. lappuse
... compiler, debugger, simulator, and other tools. Task-level behavior also provides a major and related challenge for SoC software. As mentioned above, task-level parallelism is both easy to identify in SoC applications and important to ...
... compiler, debugger, simulator, and other tools. Task-level behavior also provides a major and related challenge for SoC software. As mentioned above, task-level parallelism is both easy to identify in SoC applications and important to ...
17. lappuse
... compiler research has exploited the abovementioned parallelism in the processor architecture. Recently, the dynamic reconfiguration (explicitly parallel instruction computing [EPIC]) processor [8] has provided another degree of ...
... compiler research has exploited the abovementioned parallelism in the processor architecture. Recently, the dynamic reconfiguration (explicitly parallel instruction computing [EPIC]) processor [8] has provided another degree of ...
18. lappuse
... Compilers are equally important, and several chapters discuss compilation for size, time constraints, memory system efficiency, and other objectives. The applications and methodology section looks at sample applications such as video ...
... Compilers are equally important, and several chapters discuss compilation for size, time constraints, memory system efficiency, and other objectives. The applications and methodology section looks at sample applications such as video ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa