Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 90.
xi. lappuse
... Communication Element Modeling and Analysis 165 6.2.4 Formal Communication Element Analysis 166 6.2.5 Memory Element Modeling and Analysis 167 6.2.6 Architecture Component Modeling and Analysis: Summary 168 6.3 Process Execution ...
... Communication Element Modeling and Analysis 165 6.2.4 Formal Communication Element Analysis 166 6.2.5 Memory Element Modeling and Analysis 167 6.2.6 Architecture Component Modeling and Analysis: Summary 168 6.3 Process Execution ...
xii. lappuse
... Communication Architecture Templates 203 7.4.2 Communication Architecture Template Customization 204 Adaptive Communication Architectures 210 7.5.1 Communication Architecture Tuners 210 Communication Architectures for Energy/Battery ...
... Communication Architecture Templates 203 7.4.2 Communication Architecture Template Customization 204 Adaptive Communication Architectures 210 7.5.1 Communication Architecture Tuners 210 Communication Architectures for Energy/Battery ...
15. lappuse
... architecture. Conventional parallel programming models need to support any ... communication), the operating system (OS), and the hardware abstraction ... architecture provides a virtual machine on which the application software runs. The ...
... architecture. Conventional parallel programming models need to support any ... communication), the operating system (OS), and the hardware abstraction ... architecture provides a virtual machine on which the application software runs. The ...
20. lappuse
... architecture level. An on-chip network can be built from carefully designed components that encapsulate high-performance circuits. Packet-based communication also helps structure the application's communication. Because different ...
... architecture level. An on-chip network can be built from carefully designed components that encapsulate high-performance circuits. Packet-based communication also helps structure the application's communication. Because different ...
41. lappuse
Ahmed Jerraya, Wayne Wolf. 2.4.3. Energy. Considerations. in. Advanced. Interconnects. Network architecture heavily influences communication energy. As hinted in the previous section, shared-medium networks (busses) are currently the most ...
Ahmed Jerraya, Wayne Wolf. 2.4.3. Energy. Considerations. in. Advanced. Interconnects. Network architecture heavily influences communication energy. As hinted in the previous section, shared-medium networks (busses) are currently the most ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa