Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.–5. rezultāts no 48.
13. lappuse
... busses for specialized data transfer, a peripheral interface (PI) bus and a digital video platform (DVP) memory bus for intensive shared data transfer. This fixed memory architecture, besides the limited number and types of the ...
... busses for specialized data transfer, a peripheral interface (PI) bus and a digital video platform (DVP) memory bus for intensive shared data transfer. This fixed memory architecture, besides the limited number and types of the ...
14. lappuse
... busses, interfaces, and hardware IPs. The IP library and development tools provided by Xilinx especially support the IBM CoreConnect busses. Given the examples of commercially available MPSoC chips, we see that most of them: limit the ...
... busses, interfaces, and hardware IPs. The IP library and development tools provided by Xilinx especially support the IBM CoreConnect busses. Given the examples of commercially available MPSoC chips, we see that most of them: limit the ...
34. lappuse
... busses and point-to-point links), to complex advanced interconnects (networks on-chip [NoCs]) that are applicable to MPSoCs. Also, refer to Chapter 3 in this volume for additional material related to this section. The simplest on-chip ...
... busses and point-to-point links), to complex advanced interconnects (networks on-chip [NoCs]) that are applicable to MPSoCs. Also, refer to Chapter 3 in this volume for additional material related to this section. The simplest on-chip ...
36. lappuse
... busses. Thus, this encoding provides small energy saving for busses of typical width. 37 A solution to this problem is to partition the 2 Techniques for Designing Energy-Aware MPSoCs.
... busses. Thus, this encoding provides small energy saving for busses of typical width. 37 A solution to this problem is to partition the 2 Techniques for Designing Energy-Aware MPSoCs.
38. lappuse
... busses . For instance , DRAM address busses use a time multiplexed addressing protocol , whose transition activity can be reduced by a tailored encoding scheme , as outlined in Cheng and Pedram [ 53 ] . Further- more , several encoding ...
... busses . For instance , DRAM address busses use a time multiplexed addressing protocol , whose transition activity can be reduced by a tailored encoding scheme , as outlined in Cheng and Pedram [ 53 ] . Further- more , several encoding ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa