Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 66.
viii. lappuse
... Benini and Giovanni De Micheli 3.1 Introduction 49 3.1.1 Technology Trends 49 3.1.2 Nondeterminism in SoC Abstraction Models 50 3.1.3 A New Design Approach to SoCs 51 ix 3.2 Signal Transmission on Chip 52 3.2.1 Global Wiring Contents.
... Benini and Giovanni De Micheli 3.1 Introduction 49 3.1.1 Technology Trends 49 3.1.2 Nondeterminism in SoC Abstraction Models 50 3.1.3 A New Design Approach to SoCs 51 ix 3.2 Signal Transmission on Chip 52 3.2.1 Global Wiring Contents.
xv. lappuse
... Abstraction 364 13.2.4 Component-Based Approach 365 13.3 Design Models for Component Abstraction 367 13.3.1 Conceptual Design Flow 368 13.3.2 Virtual Architecture Model 368 13.3.3 Target Architecture Model 370 13.3.4 The Hardware ...
... Abstraction 364 13.2.4 Component-Based Approach 365 13.3 Design Models for Component Abstraction 367 13.3.1 Conceptual Design Flow 368 13.3.2 Virtual Architecture Model 368 13.3.3 Target Architecture Model 370 13.3.4 The Hardware ...
11. lappuse
... abstractions, predictability of results, and meeting design metrics are the main goals. Fast design time is very ... abstraction level is needed on the hardware side. When designers use RTL abstractions, they can produce, on average ...
... abstractions, predictability of results, and meeting design metrics are the main goals. Fast design time is very ... abstraction level is needed on the hardware side. When designers use RTL abstractions, they can produce, on average ...
12. lappuse
... abstractions are needed on the software side too. Design components for MPSoC are heterogeneous: they come from ... abstraction levels. Design steps can be grouped into two major tasks: design space exploration (hardware/software ...
... abstractions are needed on the software side too. Design components for MPSoC are heterogeneous: they come from ... abstraction levels. Design steps can be grouped into two major tasks: design space exploration (hardware/software ...
14. lappuse
... abstraction level. SOFTWARE. 1.7.1. The software for MPSoC needs to be considered from the following three viewpoints: the programmer's viewpoint, the software architecture and design reuse viewpoint, and the optimization viewpoint ...
... abstraction level. SOFTWARE. 1.7.1. The software for MPSoC needs to be considered from the following three viewpoints: the programmer's viewpoint, the software architecture and design reuse viewpoint, and the optimization viewpoint ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components concurrent configuration constraints core cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface IP core latency layer logic mapping memory meta-model methodology MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa