Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
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1.5. rezultāts no 17.
13. lappuse
... (VLIW) media processor (32-bit or 64-bit @ 100 to 300+MHz) and a MIPS core (32bit or 64-bit @ 50 to 300+MHz). It also contains a library of dedicated hardware processing units (image coprocessors, DSPs, universal asynchronous receiver ...
... (VLIW) media processor (32-bit or 64-bit @ 100 to 300+MHz) and a MIPS core (32bit or 64-bit @ 50 to 300+MHz). It also contains a library of dedicated hardware processing units (image coprocessors, DSPs, universal asynchronous receiver ...
16. lappuse
... (VLIW) and thread-level 17 parallelism statically (clustered VLIW) and dynamically (simultaneous multithreading [SMT]). 1 The What, Why, and How of MPSoCs.
... (VLIW) and thread-level 17 parallelism statically (clustered VLIW) and dynamically (simultaneous multithreading [SMT]). 1 The What, Why, and How of MPSoCs.
17. lappuse
Ahmed Jerraya, Wayne Wolf. 17. parallelism statically (clustered VLIW) and dynamically (simultaneous multithreading [SMT]). A great deal of compiler research has exploited the abovementioned parallelism in the processor architecture ...
Ahmed Jerraya, Wayne Wolf. 17. parallelism statically (clustered VLIW) and dynamically (simultaneous multithreading [SMT]). A great deal of compiler research has exploited the abovementioned parallelism in the processor architecture ...
82. lappuse
... (VLIW) execution model [149], which encodes regular parallelism in an efficient and predictable way. Efficiency is desirable from the standpoint of power, and predictability is desirable from the standpoint of real-time constraints. The ...
... (VLIW) execution model [149], which encodes regular parallelism in an efficient and predictable way. Efficiency is desirable from the standpoint of power, and predictability is desirable from the standpoint of real-time constraints. The ...
97. lappuse
... superscalar execution) for consumer electronics (e.g., set-top boxes, DVD), storage, and communications. That said, it is difficult to tie these ... VLIW/superscalar), one or. 4.4 Survey of General-Purpose 32-bit Embedded Microprocessors.
... superscalar execution) for consumer electronics (e.g., set-top boxes, DVD), storage, and communications. That said, it is difficult to tie these ... VLIW/superscalar), one or. 4.4 Survey of General-Purpose 32-bit Embedded Microprocessors.
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa