Multiprocessor Systems-on-ChipsElsevier, 2004. gada 15. okt. - 608 lappuses Modern system-on-chip (SoC) design shows a clear trend toward integration of multiple processor cores on a single chip. Designing a multiprocessor system-on-chip (MPSOC) requires an understanding of the various design styles and techniques used in the multiprocessor. Understanding the application area of the MPSOC is also critical to making proper tradeoffs and design decisions. Multiprocessor Systems-on-Chips covers both design techniques and applications for MPSOCs. Design topics include multiprocessor architectures, processors, operating systems, compilers, methodologies, and synthesis algorithms, and application areas covered include telecommunications and multimedia. The majority of the chapters were collected from presentations made at the International Workshop on Application-Specific Multi-Processor SoC held over the past two years. The workshop assembled internationally recognized speakers on the range of topics relevant to MPSOCs. After having refined their material at the workshop, the speakers are now writing chapters and the editors are fashioning them into a unified book by making connections between chapters and developing common terminology. *Examines several different architectures and the constraints imposed on them *Discusses scheduling, real-time operating systems, and compilers *Analyzes design trade-off and decisions in telecommunications and multimedia applications |
No grāmatas satura
1.–5. rezultāts no 84.
viii. lappuse
... Design 23 2.2.1 Reducing Active Energy 24 2.2.2 Reducing Standby Energy 26 2.3 Energy-Aware Memory System Design 27 ... SoC Abstraction Models 50 3.1.3 A New Design Approach to SoCs 51 ix 3.2 Signal Transmission on Chip 52 3.2.1 Global ...
... Design 23 2.2.1 Reducing Active Energy 24 2.2.2 Reducing Standby Energy 26 2.3 Energy-Aware Memory System Design 27 ... SoC Abstraction Models 50 3.1.3 A New Design Approach to SoCs 51 ix 3.2 Signal Transmission on Chip 52 3.2.1 Global ...
ix. lappuse
... Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non-Determinism Without Undermining Safety 108 4.6 Conclusions 110 x 5 Performance and Flexibility for Multiple-Processor SoC Design 113 Contents.
... Performance via Multithreading 105 4.5 Virtual Simple Architecture (VISA): Integrating Non-Determinism Without Undermining Safety 108 4.6 Conclusions 110 x 5 Performance and Flexibility for Multiple-Processor SoC Design 113 Contents.
x. lappuse
Ahmed Jerraya, Wayne Wolf. x 5 Performance and Flexibility for Multiple-Processor SoC Design 113 Chris Rowen 5.1 Introduction 113 5.2 The Limitations of Traditional ASIC Design 118 5.2.1 The Impact of SoC Integration 120 5.2.2 The ...
Ahmed Jerraya, Wayne Wolf. x 5 Performance and Flexibility for Multiple-Processor SoC Design 113 Chris Rowen 5.1 Introduction 113 5.2 The Limitations of Traditional ASIC Design 118 5.2.1 The Impact of SoC Integration 120 5.2.2 The ...
xix. lappuse
... SoC design. MPSoCs are much more complex than ASICs and so require traditionally separate disciplines to converge. Computer architecture, real-time operating systems, embedded software, computer-aided design, and circuit design are all ...
... SoC design. MPSoCs are much more complex than ASICs and so require traditionally separate disciplines to converge. Computer architecture, real-time operating systems, embedded software, computer-aided design, and circuit design are all ...
1. lappuse
... design into computer architecture. The demands placed on these chips by applications require designers to face ... (SoC). An SoC is an integrated circuit that implements most or all of the functions of a complete electronic system. The ...
... design into computer architecture. The demands placed on these chips by applications require designers to face ... (SoC). An SoC is an integrated circuit that implements most or all of the functions of a complete electronic system. The ...
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abstraction algorithms analysis application application-specific approach behavior block branch prediction buffer busses cache channel chip circuit communication architecture communication protocols compiler complex components Computer-Aided Design concurrent configuration constraints cores cycles dataflow deadline decoder Design Automation Design Automation Conference dynamic EEMBC efficient elements embedded systems encoding energy consumption event example execution FIFO FPGA function general-purpose global hardware heterogeneous IEEE implementation input instruction integrated interconnect interface latency layer logic mapping memory meta-model MoCs modules MPSoC multimedia multiple multiprocessor netlist number of processors on-chip communication optimization packet parallelism parameters performance pipeline platform port priority Proc resource RISC RTOS run-time scheduling shared shown in Figure signal simulation SoC design specification static subsystem superscalar switching Symposium synchronization synthesis system design SystemC target task techniques tion Ubicom VLIW VLSI voltage WCET wrapper Xtensa