Programmable Digital Signal Processors: Architecture: Programming, and ApplicationsYu Hen Hu CRC Press, 2001. gada 6. dec. - 456 lappuses "Presents the latest developments in the prgramming and design of programmable digital signal processors (PDSPs) with very-long-instruction word (VLIW) architecture, algorithm formulation and implementation, and modern applications for multimedia processing, communications, and industrial control." |
Saturs
1 | |
VLIW Processor Architectures and Algorithm Mappings for DSP Applications | 47 |
Multimedia Instructions in Microprocessors for Native Signal Processing | 91 |
Reconfigurable Computing and Digital Signal Processing Past Present and Future | 147 |
Parallel Architectures for Programmable Video Signal Processing | 187 |
OASIS An Optimized Code Generation Approach for Complex Instruction Set PDSPs | 243 |
Digital Signal Processing on MMX Technology | 295 |
HardwareSoftware Cosynthesis of DSP Systems | 333 |
Data Transfer and Storage Architecture Issues and Exploration in Multimedia Processors | 379 |
lndex | 427 |
Citi izdevumi - Skatīt visu
Programmable Digital Signal Processors: Architecture: Programming, and ... Yu Hen Hu Priekšskatījums nav pieejams - 2002 |
Bieži izmantoti vārdi un frāzes
3DNow actor allocation AltiVec architecture arithmetic array audio bits block buffer bytes c₁ cache chip compiler coprocessor Custom Computing Machines cycle data flow data types decoder developed digital signal processing DSP applications DSP systems dynamic edge efficient encoder example execution floating-point FPGA functional units general-purpose hardware IDCT IFGALU implementation input instruction set integer Intel Intel Corporation interface latency load load/store logic macroblock mapping memory microprocessors MMX instructions MMX technology modular arithmetic MPEG multimedia multiple multiprocessor node on-chip operands operations optimization output packed parallelism partitioning PDSPs performance pipelining pixel Proceedings real-time reconfigurable computing result RISC saturation saturation arithmetic scheduling Section shift shown in Figure SIMD software pipelining source registers specification SRAM subwords synchronization Table target register techniques template Texas Instruments tion transformations unsigned vector VLIW VLIW processors VSPs Xilinx
Populāri fragmenti
184. lappuse - M. Wan, H. Zhang. V. George, M. Benes, A. Abnous, V. Prabhu, and J. Rabaey, "Design methodology of a lowenergy reconfigurable single-chip DSP system,
377. lappuse - M. Pankert, O. Mauss, S. Ritz, and H. Meyr, Dynamic data flow and control flow in high level DSP code synthesis, Proceedings of the International Conference on Acoustics, Speech, and Signal Processing, Adeliade, Australia, 1994.
43. lappuse - Liu, CL, Layland, JW, Scheduling Algorithms for Multiprogramming in a HardReal-Time Environment, Journal of the ACM, Vol.
336. lappuse - For any v (AT nXO-fw }, there are a directed path from u to v and a directed path from v to u. When the edge directions are ignored, the path from M to v is an alternating path with respect to M ' and begins with an edge not in M'.
377. lappuse - PP Vaidyanathan Multirate Systems and Filter Banks. Englewood Cliffs, NJ: Prentice-Hall, 1993. [11] M. Vetterli and J. Kovacevic, Wavelets and Subband Coding, Prentice Hall, 1995.
241. lappuse - JTJ van Eijndhoven, FW Sijstermans, KA Vissers, E.-JD Pol, MJA Tromp, P. Struik, RHJ Bloks, P. van der Wolf, AD Pimentel, and HPE Vranken. TriMedia CPU64 Architecture.
290. lappuse - K..W. Leary and W. Waddington, "DSP/C: A Standard High Level Language for DSP and Numeric Processing", Proceedings of the International Conference on Acoustics, Speech and Signal Processing, IEEE, 1990, pp.