System-Level Design Techniques for Energy-Efficient Embedded SystemsSpringer Science & Business Media, 2004 - 194 lappuses System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone. |
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Saturs
INTRODUCTION | 1 |
11 Embedded System Design Flow | 2 |
12 System Specification Step A | 5 |
13 CoSynthesis Step B | 6 |
14 Hardware and Software Synthesis Step C | 14 |
15 Book Overview | 17 |
BACKGROUND | 19 |
22 Energy Minimisation Techniques | 24 |
51 Preliminaries | 100 |
52 Motivational Examples | 104 |
53 Previous Work | 107 |
54 Problem Formulation | 109 |
55 CoSynthesis of EnergyEfficient MultiMode Systems | 111 |
MultiMode | 122 |
57 Concluding Remarks | 130 |
DYNAMIC VOLTAGE SCALING FOR CONTROL FLOWINTENSIVE APPLICATIONS | 133 |
23 Energy Dissipation of Communication Links | 29 |
24 Further Readings | 30 |
25 Concluding Remarks | 33 |
POWER VARIATIONDRIVEN DYNAMIC VOLTAGE SCALING | 35 |
31 Motivation | 36 |
32 Algorithms for Dynamic Voltage Scaling | 44 |
EnergyGradient based Dynamic Voltage Scaling | 50 |
34 Concluding Remarks | 58 |
OPTIMISATION OF MAPPING AND SCHEDULING FOR DYNAMIC VOLTAGE SCALING | 61 |
41 Schedule Optimisation | 62 |
42 Optimisation of Task and Communication Mapping | 81 |
43 Optimisation of Allocation | 94 |
44 Concluding Remarks | 97 |
ENERGYEFFICIENT MULTIMODE EMBEDDED SYSTEMS | 99 |
62 Schedule Table for CTGs | 135 |
63 Dynamic Voltage Scaling for CTGs | 136 |
64 Voltage Scaling Technique for CTGs | 139 |
65 Conclusions | 148 |
LOPOCOS A PROTOTYPE LOW POWER COSYNTHESIS TOOL | 151 |
72 LOPOCOS | 157 |
73 Concluding Remarks | 172 |
CONCLUSION | 173 |
81 Summary | 174 |
82 Future Directions | 177 |
181 | |
193 | |
Citi izdevumi - Skatīt visu
System-Level Design Techniques for Energy-Efficient Embedded Systems Marcus T. Schmitz,Bashir M. Al-Hashimi,Petru Eles Ierobežota priekšskatīšana - 2006 |
System-Level Design Techniques for Energy-Efficient Embedded Systems Marcus T. Schmitz,Bashir M. Al-Hashimi,Petru Eles Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
active allocated ASIC Atmin average power benchmark calculated Chapter co-synthesis communication mapping computational Computer-Aided Design condition values consider constraints core Design Automation Conference distributed embedded systems DVS-enabled DVS-PEs dynamic power dynamic voltage scaling EE-GLSA embedded systems encoder energy consumption energy dissipation energy minimisation energy reduction energy savings energy-efficient energy-gradient epst example finite state machine fixed power model FPGA genetic algorithm genetic list scheduling given ICMSP IDCT IDLE IEEE implementation introduced iterative LOPOCOS mapping and scheduling mapping string mode execution probabilities nominal supply voltage operational mode performance power consumption power dissipation power variation model processing elements processor proposed PV-DVS Radio Link Control run-time schedule optimisation schedule table scheduling algorithm scheduling and mapping scheduling technique Section shown in Figure smart phone solution step synthesis system-level task 73 task execution task graph task mapping task type tasks and communications tion track Vmax
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