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" H. Kojima, S. Tanaka, and K. Sasaki, "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry, "
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication - 823. lappuse
autors: Hubert Kaeslin - 2008 - 845 lapas
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Interconnect-Centric Design for Advanced SOC and NOC

Jari Nurmi - 2004 - 474 lapas
...1.2GHz Alpha microprocessor", ISSCC Digest of Technical Papers, 2001, Pg 402-403 7. H. Kojima, et al, - "Half-swing clocking scheme for 75% power saving in...circuitry", IEEE Journal of Solid-State Circuits, April 1995, Pg 432 -435 8. H. Kawaguchi, T. Sakurai, . "A reduced clock-swing flip-Hop (RCSFF) for...
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Processor Design: System-On-Chip Computing for ASICs and FPGAs

Jari Nurmi - 2007 - 526 lapas
...Architecture Research. Computer Architecture Letters, 1(1):7 234. Kojima H, Tanaka S, Sasaki K (1995) Half-Swing Clocking Scheme for 75% Power Saving in...Clocking Circuitry. IEEE Journal of Solid-State Circuits, 30(4):432^135 235. Kongetira P, Aingaran K, Olukotun K (2005) Niagara: A 32-Way Multithreaded Spare...
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