The Designer's Guide to VHDL
Morgan Kaufmann, 2002 - 759 lappuses
"The second edition of The Designer's Guide to VHDL sets a new standard in VHDL texts. I am certain that you will find it a very valuable addition to your library." --From the foreword by Paul Menchini, Menchini & AssociatesSince the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.Features: Details how the new standard allows for increased portability across tools. Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design. Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters. Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
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E VHDL Syntax 683
Scalar Data Types and Operations
Summary of Loop Statements
Component Instantiation and Port Maps
A Pipelined Multiplier Accumulator
Packages and Use Clauses
A BitVector Arithmetic Package
G Answers to Exercises 703
Components and Configurations
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actual addition alias allows applied architecture body array assertion association begin behavioral binding bit_vector boolean called carry changes Chapter character clause clock complex component instance condition configuration connected constant contains corresponding counter defined delay described determine digit downto driver elements end architecture end entity end process entity declaration example executed expression false formal function identifier IEEE implementation indication initial input instantiation integer interface label length literal logic look loop mode module multiplier natural Note object operand operators outline output overflow package parameter perform port map position procedure produce range record refer represent resolved result selected shown in Figure shows signed simulation specify statement structural subtype syntax rule tion transaction true unit unsigned variable vector VHDL wait write