The Designer's Guide to VHDLMorgan Kaufmann, 2002 - 759 lappuses "The second edition of The Designer's Guide to VHDL sets a new standard in VHDL texts. I am certain that you will find it a very valuable addition to your library." --From the foreword by Paul Menchini, Menchini & AssociatesSince the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.Features: Details how the new standard allows for increased portability across tools. Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design. Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters. Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD. |
No grāmatas satura
1.5. rezultāts no 77.
iv. lappuse
... Logic System for VHDL Model Interoperability ( Std_logic_1164 ) , Copyright 1993 by IEEE . Section C.2 of Appendix C reprinted with permission from IEEE Std . 1076.3-1997 , IEEE Standard VHDL Synthe- sis Packages , Copyright 1997 by ...
... Logic System for VHDL Model Interoperability ( Std_logic_1164 ) , Copyright 1993 by IEEE . Section C.2 of Appendix C reprinted with permission from IEEE Std . 1076.3-1997 , IEEE Standard VHDL Synthe- sis Packages , Copyright 1997 by ...
xiv. lappuse
... Logic System 245 Standard VHDL Synthesis Packages 246 Standard VHDL Mathematical Packages 250 Exercises 255 9 Aliases 9.1 Aliases for Data Objects 258 9.2 Aliases for Non - Data Items 261 231 257 Exercises 264 10 Case Study : A Bit ...
... Logic System 245 Standard VHDL Synthesis Packages 246 Standard VHDL Mathematical Packages 250 Exercises 255 9 Aliases 9.1 Aliases for Data Objects 258 9.2 Aliases for Non - Data Items 261 231 257 Exercises 264 10 Case Study : A Bit ...
xv. lappuse
... Test - Bench Architecture Body and Configuration 413 15.4 A Register - Transfer - Level Model 416 The Arithmetic and Logic Unit 417 The Registers 421 349 373 The Register File 425 The Multiplexer 426 The Extenders 427 Contents XV.
... Test - Bench Architecture Body and Configuration 413 15.4 A Register - Transfer - Level Model 416 The Arithmetic and Logic Unit 417 The Registers 421 349 373 The Register File 425 The Multiplexer 426 The Extenders 427 Contents XV.
xvii. lappuse
... Logic Values 642 A.3 Modeling Combinatorial Logic 643 A.4 Modeling Sequential Logic 644 A.5 VHDL Modeling Restrictions 650 B C The Predefined Package Standard IEEE Standard Packages C.1 Contents xvii.
... Logic Values 642 A.3 Modeling Combinatorial Logic 643 A.4 Modeling Sequential Logic 644 A.5 VHDL Modeling Restrictions 650 B C The Predefined Package Standard IEEE Standard Packages C.1 Contents xvii.
xviii. lappuse
... Logic System 659 C.2 Standard 1076.3 VHDL Synthesis Packages 662 C.3 Standard 1076.2 VHDL Mathematical Packages 665 Ꭰ Related Standards D.1 IEEE VHDL Standards 671 E D.2 Other Design Automation Standards VHDL Syntax E.1 Design File 685 ...
... Logic System 659 C.2 Standard 1076.3 VHDL Synthesis Packages 662 C.3 Standard 1076.2 VHDL Mathematical Packages 665 Ꭰ Related Standards D.1 IEEE VHDL Standards 671 E D.2 Other Design Automation Standards VHDL Syntax E.1 Design File 685 ...
Saturs
1 | 4 |
Exercises | 26 |
Exercises | 54 |
4 | 60 |
5 | 73 |
Exercises | 83 |
Exercises | 105 |
Basic Modeling Constructs | 107 |
Exercises 611 | 227 |
Packages and Use Clauses | 231 |
Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Resolved Signals | 285 |
G Answers to Exercises 703 | 301 |
13 | 315 |
Packaging Components | 321 |
21 | 137 |
A Pipelined Multiplier Accumulator | 167 |
Subprograms | 195 |
Exercises | 344 |
The DLX Computer System | 373 |
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actual parameter adder alias architecture body array type assertion statement behavioral model binary bit_vector boolean Chapter clause clock clock signal component instance condition configuration declaration constant counter data input defined delay described downto EBNF elements end entity end loop end process entity and architecture entity declaration enumeration type example executed exit expression flipflop floating-point formal parameter formal verification function identifier implementation index range input port instantiation integer interface keyword label left operand literals logic mem_read module opcode operand operators output ports overflow package declaration physical type port map predefined process statement reg4 represent reset result return statement sequential statements shown in Figure sign bit signal assignment statement simple_expression simulation specify standard-logic std_logic std_ulogic structural subprogram subtype syntax rule test bench transaction type conversion type declaration unit unsigned variable vector VHDL wait statement write xnor zero