System-Level Design Techniques for Energy-Efficient Embedded SystemsSpringer, 2006. gada 16. janv. - 194 lappuses System-Level Design Techniques for Energy-Efficient Embedded Systems addresses the development and validation of co-synthesis techniques that allow an effective design of embedded systems with low energy dissipation. The book provides an overview of a system-level co-design flow, illustrating through examples how system performance is influenced at various steps of the flow including allocation, mapping, and scheduling. The book places special emphasis upon system-level co-synthesis techniques for architectures that contain voltage scalable processors, which can dynamically trade off between computational performance and power consumption. Throughout the book, the introduced co-synthesis techniques, which target both single-mode systems and emerging multi-mode applications, are applied to numerous benchmarks and real-life examples including a realistic smart phone. |
Saturs
| 2 | |
BACKGROUND | 19 |
POWER VARIATIONDRIVEN DYNAMIC VOLTAGE SCALING | 35 |
the fixed power model using EVENDVS approach | 52 |
Concluding Remarks | 61 |
Experimental results obtained using the fixed power | 77 |
ample | 90 |
NODVS Nominal EVENDVS and PVDVS | 92 |
6 | 133 |
A LOW POWER COSYNTHESIS TOOL 7 1 7 2 7 3 | 151 |
17 | 156 |
30 | 162 |
CONCLUSION | 173 |
References | 181 |
77 | 186 |
Index | 187 |
Citi izdevumi - Skatīt visu
System-Level Design Techniques for Energy-Efficient Embedded Systems Marcus T. Schmitz,Bashir M. Al-Hashimi,Petru Eles Ierobežota priekšskatīšana - 2004 |
System-Level Design Techniques for Energy-Efficient Embedded Systems Marcus T. Schmitz,Bashir M. Al-Hashimi,Petru Eles Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
According achieved active additional algorithm allocated allows application approach architecture average power benchmark calculated Chapter co-synthesis column communication communication mapping compared components computational condition values consider consideration constraints cores corresponds cost deadline decoder depending distributed dynamic voltage scaling edges effective embedded systems energy consumption energy dissipation energy-efficient example experiments exploited extension functionality further genetic given hardware hence implementation improve increase individuals instance introduced list scheduling LOPOCOS minimisation mode execution probabilities multi-mode needs Nevertheless Note observed operational mode optimisation outlined performance possible power consumption power dissipation presented problem processing elements processor produced proposed reduced represents respectively run-time savings schedule table scheduling selected shown in Figure shows single slack solution space specification static step string supply voltage synthesis Table taking task graph task mapping technique tion track transition