The Massively Parallel Processing System JUMP-1Hidehiko Tanaka, Yōichi Muraoka Ohmsha, 1996 - 235 lappuses The work features the development of the fundamental technologies for massively parallel processing, covering research on the applications, the language, the operating system and the hardware architecture. Also the present status and future plans are addressed. The following topics are discussed in the section on applications: the MGCG Method; Parallelization of FEM; Modeling of Group Behaviors; Parallel Visualization; Functional Memory Type Parallel Processing; a Parallel Reduction Algorithm and Combination Algorithm. As for the programming languages, the SIMD-Based Language NCX, the Dataflow-based Language V and the Parallel Object-Oriented Language A-NETL are discussed. In the chapter on operating systems, the subjects Design Philosophy and Objectives; COS Software Architecture and Elements of the Operating System are - amongst others - addressed. Finally, the part on hardware architecture covers an Overview of the JUMP-1 System; Memory Architecture; Network Architecture; I/O Architecture and Implementation Issues. Massively parallel processing is expected to play a crucial role in the development of almost all advanced technologies for the 21st century. This book is intended to serve a large variety of researchers in the area of parallel computing. |
No grāmatas satura
1.–3. rezultāts no 85.
136. lappuse
... implementation strategy is to im- plement them on top of lower - level message passing primitives with heavy ker- nel intervention , resulting in considerable overhead and loss of performance . Implementation on COS / JUMP - 1 , on the ...
... implementation strategy is to im- plement them on top of lower - level message passing primitives with heavy ker- nel intervention , resulting in considerable overhead and loss of performance . Implementation on COS / JUMP - 1 , on the ...
165. lappuse
... implement parallel execution . In this implementation , UX servers are just like hosts connected by a high - speed network . Each UX server is indepen- dent . Since multiple UX servers have to cooperate , performance may not be ...
... implement parallel execution . In this implementation , UX servers are just like hosts connected by a high - speed network . Each UX server is indepen- dent . Since multiple UX servers have to cooperate , performance may not be ...
220. lappuse
... Implementation issues are as important as architectural design for con- structing practical MPP systems with more ... implementation . • Power consumption of latest MPUs has increased and cooling an MPU chip is already problematical ...
... Implementation issues are as important as architectural design for con- structing practical MPP systems with more ... implementation . • Power consumption of latest MPUs has increased and cooling an MPU chip is already problematical ...
Citi izdevumi - Skatīt visu
The Massively Parallel Processing System JUMP-1 Hidehiko Tanaka,Yōichi Muraoka Priekšskatījums nav pieejams - 1996 |
Bieži izmantoti vārdi un frāzes
A-NETL address space agent instance algorithm allocation application program architecture array block buffer cluster coherence communication data-parallel distributed shared memory double-word efficient equation example execution expression Fibonacci tree field FIFO fine-grained FMPP function global grid hardware highly parallel hypercube implementation interface L2 cache language latency mapping massively parallel computer massively parallel processing mechanism member stream memory access memory management memory objects memory system mesh MGCG method Micro Kernel MIMD mono multigrid method multiple network address Neumann boundary condition nodes operating system page table parallel machines parallel programs parallel stream partition performance pixel problem Proc processing elements protocol provides PUX server queue reduction computation shown in Figure SIMD simulation STAFF-Link statement substructure synchronization task topology torus toruses update user-level threads variable vector virtual processors voxel