Rapid Thermal and Other Short-time Processing Technologies II: Proceedings of the International SymposiumDim-Lee Kwong, Electrochemical Society. Electronics Division, Electrochemical Society. Dielectric Science and Technology Division, Electrochemical Society. High Temperature Materials Divisions The Electrochemical Society, 2001 - 438 lappuses "Electronics, Dielectric Science and Technology, and High Temperature Materials Divisions." |
No grāmatas satura
1.–5. rezultāts no 100.
x. lappuse
... Silicon L. Shao , X. M. Lu , X. M. Wang , J. R. Liu , and W. K. Chu 305 32. Fundamental Issues in Rapid Thermal Annealing ( RTA ) , Spike RTA and Excimer Laser Annealing ( ELA ) for the Formation of Shallow p + / n Junctions Y. F. Chong ...
... Silicon L. Shao , X. M. Lu , X. M. Wang , J. R. Liu , and W. K. Chu 305 32. Fundamental Issues in Rapid Thermal Annealing ( RTA ) , Spike RTA and Excimer Laser Annealing ( ELA ) for the Formation of Shallow p + / n Junctions Y. F. Chong ...
5. lappuse
... silicon gate electrode 5.5 1.5 ** Spacer ( oxide / nitride ) 9.0 1.0 * Salicide block ( oxide / nitride ) 9.0 1.0 * Window etch stop ( nitride ) 4.5 1.0 Total 57.5 10.0 * Integrated low temperature oxide and nitride processes ...
... silicon gate electrode 5.5 1.5 ** Spacer ( oxide / nitride ) 9.0 1.0 * Salicide block ( oxide / nitride ) 9.0 1.0 * Window etch stop ( nitride ) 4.5 1.0 Total 57.5 10.0 * Integrated low temperature oxide and nitride processes ...
8. lappuse
... Silicon 8.16 8.58 Spacer ( oxide / nitride ) 12.48 8.53 Salicide block 12.48 8.53 ( oxide / nitride ) Window etch stop ( nitride ) 6.27 Total 6.40 43.64 36.88 1 . Low thermal budget processes The down scaling of gate dielectric ...
... Silicon 8.16 8.58 Spacer ( oxide / nitride ) 12.48 8.53 Salicide block 12.48 8.53 ( oxide / nitride ) Window etch stop ( nitride ) 6.27 Total 6.40 43.64 36.88 1 . Low thermal budget processes The down scaling of gate dielectric ...
15. lappuse
... silicon layer . The changing growth rate is caused by emissivity variations giving rise to temperature changes [ 1-5 ] . In this study , the same epi growing conditions is applied to patterned wafers with a different field oxide ...
... silicon layer . The changing growth rate is caused by emissivity variations giving rise to temperature changes [ 1-5 ] . In this study , the same epi growing conditions is applied to patterned wafers with a different field oxide ...
19. lappuse
... Silicon SIMS areas Fig . 5. The layout of the mask , showing the large squares , the distribution of silicon and oxide fields inside the squares and the surroundings of the SIMS area . As shows Fig . 5 the wafer is divided into 10 large ...
... Silicon SIMS areas Fig . 5. The layout of the mask , showing the large squares , the distribution of silicon and oxide fields inside the squares and the surroundings of the SIMS area . As shows Fig . 5 the wafer is divided into 10 large ...
Saturs
15 | |
20 | |
23 | |
33 | |
41 | |
49 | |
61 | |
67 | |
221 | |
231 | |
239 | |
245 | |
261 | |
297 | |
305 | |
311 | |
79 | |
87 | |
97 | |
105 | |
106 | |
113 | |
121 | |
129 | |
147 | |
157 | |
163 | |
171 | |
197 | |
205 | |
211 | |
321 | |
337 | |
345 | |
353 | |
363 | |
371 | |
379 | |
393 | |
401 | |
409 | |
420 | |
421 | |
429 | |
435 | |
Bieži izmantoti vārdi un frāzes
activation ambient amorphous annealing Appl applications atoms boron carrier channel characteristics characterization CMOS compared concentration constant curve defects density dependence deposited device diffusion dopant doping effect electrical Electron energy fabrication Figure films formation gate dielectric gate electrode gate oxide gate stack grown growth heating HfO2 high-k higher implantation important improved increase indicates integration interface junction depth laser layer leakage current Lett limited lower material measured metal method nitride observed obtained oxygen peak performance phase Phys physical plate produced properties ramp range rapid thermal reduced reflectivity samples scaling Semiconductor shallow sheet resistance shown shows silicide silicon SIMS SiO2 spike step stress structure substrate surface Table techniques temperature thermal budget Thermal Processing thickness thin transistor uniformity values various voltage wafer ZrO2
Populāri fragmenti
205. lappuse - AND DL KWONG Microelectronics Research Center, Department of Electrical and Computer Engineering The University of Texas at Austin, Austin, TX...
378. lappuse - T Morimoto, T Ohguro, HS Momose, T linuma, I Kunishima, K Suguro, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. Self-aligned nickel-mono-silicide technology for high-speed deep submicrometer logic CMOS ULSI.
283. lappuse - T. Ghani, K. Mistry, P. Packan, S. Thompson, M. Stettler, S. Tyagi, and M. Bohr, "Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors,
319. lappuse - PA Stolk, H.-J. gossmann, DJ Eaglesham, DC Jacobson, CS Rafferty, GH Gilmer, M. Jaraiz, JM Poate, HS Luftman, and T. E. Haynes, Appl.
369. lappuse - T Morimoto, HS Momose, T linuma, I Kunishima, K Suguro, H Okano, I Katakabe, H Nakajima, M Tsuchiaki, M Ono, Y Katsumata, and H Iwai. A NiSi salicide technology for advanced logic devices.
70. lappuse - K-cc line at 1.54A) cooled with water. A computer controlled stabilized high voltage supply is used at 40KV, 30mA. All safety relative to x-rays has been included. The beam is defined perpendicular to sample surface using Seller slits located just after the x-ray tube. The beam divergence is limited by interchangeable slits (or a parabolic multilayer mirror as option). A curved graphite crystal is used to monochromatize the x-ray beam after reflection on the sample surface. Standard sample holder...
283. lappuse - S.-H. Lo. DA Buchanan. Y. Taur, and W. Wang. "Quantummechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's,
72. lappuse - In all the cases, after total reflection at very grazing angle, the X-ray beam goes through the sample and the reflectance decreases rapidly when the grazing angle is increasing. The angular position of the total reflection threshold is related to the mean density value of the sample. With these very thin layers it cannot be used to deduce valuable information.
284. lappuse - L. Kang, BH Lee, W.-J. Qi, Y. Jeon, R. Nieh, S. Gopalan, K. Onishi and JC Lee, IEEE Electron Device Letters, 21,181 (2000).
311. lappuse - Department of Electrical and Computer Engineering, National University of Singapore, 4, Engineering Drive 3, Singapore 1 17576 ABSTRACT Experiments on three-terminal 'dotted-I...