Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, ProceedingsSpringer Science & Business Media, 2007. gada 21. aug. - 583 lappuses th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript. |
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1.–5. rezultāts no 24.
49. lappuse
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68. lappuse
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69. lappuse
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146. lappuse
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Saturs
SystemLevel ApplicationSpecific NoC Design for Network and Multimedia Applications | 1 |
Fast and Accurate Embedded Systems Energy Characterization Using Nonintrusive Measurements | 10 |
A Flexible GeneralPurpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms | 20 |
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture | 31 |
Template Vertical DictionaryBased Program Compression Scheme on the TTA | 43 |
Asynchronous Functional Coupling for Low Power Sensor Network Processors | 53 |
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs | 64 |
LowPower Content Addressable Memory With ReadWrite and Matched Mask Ports | 75 |
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant CryptoChips | 330 |
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA | 340 |
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform | 352 |
The Energy Scalability of WaveletBased Scalable Video Decoding | 363 |
Direct Memory Access Optimization in WirelessTerminals for Reduced Memory Latency and EnergyConsumption | 373 |
Exploiting Input Variations for Energy Reduction | 384 |
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates | 394 |
Static Power Consumption in CMOS Gates Using Independent Bodies | 404 |
The Design and Implementation of a Power Efficient Embedded SRAM | 86 |
Design of a Linear Power Amplifier with 15V PowerSupply Using ALADIN | 97 |
Settling Time Minimization of Operational Amplifiers | 107 |
LowVoltage LowPower CurvatureCorrected Voltage Reference Circuit Using DTMOSTs | 117 |
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations | 125 |
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation | 138 |
A Statistical Approach to the TimingYield Optimization of Pipeline Circuits | 148 |
A Novel GateLevel NBTI Delay Degradation Model with Stacking Effect | 160 |
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RTComponents | 171 |
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology | 181 |
DesignIn Reliability for 9065nm CMOS Nodes Submitted to HotCarriers and NBTI Degradation | 191 |
Clock Distribution Techniques for LowEMI Design | 201 |
Crosstalk Waveform Modeling Using Wave Fitting | 211 |
Weakness Identification for Effective Repair of Power Distribution Network | 222 |
New Adaptive Encoding Schemes for Switching Activity Balancing in OnChip Buses | 232 |
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Submicron Interconnects | 242 |
Soft ErrorAware Power Optimization Using Gate Sizing | 255 |
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices | 268 |
RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating | 278 |
Functional Verification of Low Power Designs at RTL | 288 |
An Improved XScale Power Simulator | 300 |
Low Power Elliptic Curve Cryptography | 310 |
Design and Test of Selfchecking AsynchronousControl Circuit | 320 |
Highlights for Low Voltage Design | 413 |
On TwoPronged PowerAware Voltage Scheduling for Multiprocessor RealTime Systems | 423 |
A Case Study on SIMD Shufflers | 433 |
Optimization for RealTime Systems with Nonconvex Power Versus Speed Models | 443 |
TripleThreshold Static Power Minimization in HighLevel Synthesis of VLSI CMOS | 453 |
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits | 463 |
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates | 474 |
A Platform for Mixed HWSW AlgorithmSpecifications for the Exploration of SW and HW Partitioning | 485 |
Fast Calculation of Permissible SlowdownFactors for Hard RealTime Systems | 495 |
Design Methodology and Software Tool for Estimation of Multilevel Instruction Cache Memory Miss Rate | 505 |
A Statistical Model of Logic Gates for Monte CarloSimulation Including OnChip Variations | 516 |
Switching Activity Reduction of MACBased FIR Filters with Correlated Input Data | 526 |
Performance of CMOS and FloatingGate FullAdders Circuits at Subthreshold Power Supply | 536 |
LowPower Digital Filtering Based on the Logarithmic Number System | 546 |
A Power Supply Selector for Energy and AreaEfficient Local Dynamic Voltage Scaling | 556 |
Dependability Evaluation of TimeRedundancy Techniques in Integer Multipliers | 566 |
Design and Industrialization Challenges of Memory Dominated SOCs | 576 |
A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies | 577 |
Analog Power Modelling | 578 |
Technological Trends Design Constraints and Design Implementation Challenges in Mobile Phone Platforms | 579 |
System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters | 580 |
581 | |
Citi izdevumi - Skatīt visu
Integrated Circuit and System Design. Power and Timing Modeling ... Nadine Azemard Ierobežota priekšskatīšana - 2007 |
Integrated Circuit and System Design. Power and Timing Modeling ... Nadine Azemard,Lars Svensson Ierobežota priekšskatīšana - 2007 |
Integrated Circuit and System Design. Power and Timing Modeling ... Nadine Azemard,Lars Svensson Priekšskatījums nav pieejams - 2007 |
Bieži izmantoti vārdi un frāzes
algorithm analysis application architecture asynchronous circuits Azemard benchmark Berlin Heidelberg 2007 cache capacitance clock CMOS component Computer configuration constraints critical path cycles decoder delay design flow differential power analysis dual rail dynamic power elliptic curve embedded embedded systems encoding energy consumption equation error estimation evaluation execution FPGA frequency function gate graph hardware HDL module IEEE implementation increase input instruction latches linear LNCS logic logic gate loop low power low-power memory methodology microprocessor NBTI netlist node operation optimization output parameters PATMOS performance platform PMOS power consumption power dissipation Proc processor proposed pulse reconfigurable reduce scheduling shown signal simulation SRAM static power static timing analysis statistical subthreshold subthreshold leakage supply voltage Svensson Eds switching synthesis Table task techniques temperature threshold voltage tool transistor transition variations vector Verilog VLSI worst-case execution