High Performance Embedded Architectures and Compilers: Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, ProceedingsPer Stenström, Michel Dubois, Manolis Katevenis, Rajiv Gupta, Theo Ungerer Springer Science & Business Media, 2008. gada 15. janv. - 400 lappuses This highly relevant and up-to-the-minute book constitutes the refereed proceedings of the Third International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2008, held in Göteborg, Sweden, January 27-29, 2008. The 25 revised full papers presented together with 1 invited keynote paper were carefully reviewed and selected from 77 submissions. The papers are organized into topical sections on a number of key subjects in the field. |
Saturs
Supercomputing for the Future Supercomputing from the Past Keynote | 5 |
Part I Multithreaded and Multicore Processors | 8 |
A Multithreaded RISC Architecture for Embedded RealTime Processing | 9 |
Message Passing on Multicore Processors with OnChip Interconnect | 22 |
A Case Study of the Cell BE | 38 |
Part IIaReconfigurable ASIP | 53 |
BRAMLUT Tradeoff on a Polymorphic DES Design | 55 |
Architecture Enhancements for the ADRES CoarseGrained Reconfigurable Array | 66 |
COmpiler Framework for EnergyAware Exploration | 192 |
Integrated CPU Cache Power Management in Multiple Clock Domain Processors | 209 |
VariationAware Software Techniques for Cache Leakage Reduction Using ValueDependence of SRAM Leakage Due to WithinDie Process Variation | 224 |
Part V HighPerformance Processors | 240 |
The Significance of Affectors and Affectees Correlations for Branch Prediction | 241 |
A Low Cost CheckpointRestore Accelerator | 258 |
A First Approach to the Loop Processor Architecture | 273 |
Collection and Analysis | 288 |
Implementation of an UWB ImpulseRadio Acquisition and Despreading Algorithm on a Low Power ASIP | 82 |
Part IIbCompiler Optimizations | 97 |
Fast Bounds Checking Using Debug Register | 98 |
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis | 114 |
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems | 130 |
Part III Industrial Processors and Application Parallelization | 145 |
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions | 147 |
Experiences with Parallelizing a Bioinformatics Program on the Cell BE | 161 |
Drug Design Issues on the Cell BE | 176 |
Part IV PowerAware Techniques | 191 |
Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm | 289 |
Methodology and Accuracy | 305 |
Characterizing TimeVarying Program Behavior | 320 |
Part VII Optimizing Memory Performance | 335 |
MLPAware Dynamic Cache Partitioning | 337 |
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture | 353 |
Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory | 369 |
Preventing Loop Blockings in the Instruction Cache | 384 |
| 398 | |
Citi izdevumi - Skatīt visu
High Performance Embedded Architectures and Compilers: Third International ... Per Stenström,Michel Dubois,Manolis Katevenis,Rajiv Gupta,Theo Ungerer Ierobežota priekšskatīšana - 2008 |
High Performance Embedded Architectures and Compilers: Third International ... Per Stenström,Michel Dubois,Manolis Katevenis,Rajiv Gupta,Theo Ungerer Priekšskatījums nav pieejams - 2009 |
High Performance Embedded Architectures and Compilers: Third International ... Per Stenström,Michel Dubois,Manolis Katevenis,Rajiv Gupta,Theo Ungerer Priekšskatījums nav pieejams - 2008 |
Bieži izmantoti vārdi un frāzes
16-bit instructions affectors and affectees algorithm application array bounds checking average basic blocks benchmarks Boud bounds checking branch prediction buffer bytecode cache misses Cell Clustal cluster compiler optimizations complex configuration control flow control flow graph core correlation cycle components debug register domain dynamic edge embedded embedded systems energy-delay entry execution fetch packet Figure flash memories flow graph front-end FTDock FU FU FU function hardware HiPEAC implementation improvement inlining input instruction cache interval iteration L2 cache LAM/MPI latency leakage loop window memory MMGP multicore multiple multithreaded NAND flash overhead paper parallel partition performance phase behavior phase predictability pipeline POWER5 predictor proposed Qemu reduce register file renamed repair point rMPI scheduling Section sequence shows SIMD SimPoint simulation speedup STROB superscalar Table techniques thread TROB Valgrind vector VLIW