Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 66.
26. lappuse
... verification is required. This approach allows the verification engineer to work on smaller components before building up to the system level (for more detail, see Chapter 2, Section 2.1). The verification plan contains sections for each ...
... verification is required. This approach allows the verification engineer to work on smaller components before building up to the system level (for more detail, see Chapter 2, Section 2.1). The verification plan contains sections for each ...
40. lappuse
... verification team simulates the entire start-up sequence of the chip. The well-defined interface of a chip ... components. The verification focus at the system level is that of ... verification levels to 40 Chapter 2 s Verification Flow.
... verification team simulates the entire start-up sequence of the chip. The well-defined interface of a chip ... components. The verification focus at the system level is that of ... verification levels to 40 Chapter 2 s Verification Flow.
41. lappuse
... verification levels to use is not as easy as it may seem. Although six levels of hardware verification were described ... components need focus. If a portion of function is new (versus function inherited from previous designs) or complex ...
... verification levels to use is not as easy as it may seem. Although six levels of hardware verification were described ... components need focus. If a portion of function is new (versus function inherited from previous designs) or complex ...
73. lappuse
... verification components and their interactions). In addition, this chapter covers the depth to which a verification team needs to understand the functions they are verifying in order to create a robust set of verification components ...
... verification components and their interactions). In addition, this chapter covers the depth to which a verification team needs to understand the functions they are verifying in order to create a robust set of verification components ...
75. lappuse
... verification engineer should not model the entire behavior of the ... verification. The stimulus engine must drive what the DUV is capable of accepting and not ... components must understand the complete interface protocol; that is, they ...
... verification engineer should not model the entire behavior of the ... verification. The stimulus engine must drive what the DUV is capable of accepting and not ... components must understand the complete interface protocol; that is, they ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL