Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
|
No grāmatas satura
1.5. rezultāts no 80.
73. lappuse
... components) that comprise the verification environment, and examines the driver and checker concepts that were ... test bench. In general, a test bench is all the code used to create, observe, and check a pre-determined s FIGURE 3.1 ...
... components) that comprise the verification environment, and examines the driver and checker concepts that were ... test bench. In general, a test bench is all the code used to create, observe, and check a pre-determined s FIGURE 3.1 ...
74. lappuse
... test bench has no inputs or outputs. It is effectively a model of the universe from the design-under-verification (DUV) standpoint. The verification engineer must create the code for the components of this test bench universe, and the ...
... test bench has no inputs or outputs. It is effectively a model of the universe from the design-under-verification (DUV) standpoint. The verification engineer must create the code for the components of this test bench universe, and the ...
75. lappuse
... possible ways. Without full protocol stimulus capability, the model is incomplete. S t i m u l u s Sometimes these verification components have configuration settings that allow the. 3.1 Basic Verification Environment: A Test Bench 75.
... possible ways. Without full protocol stimulus capability, the model is incomplete. S t i m u l u s Sometimes these verification components have configuration settings that allow the. 3.1 Basic Verification Environment: A Test Bench 75.
76. lappuse
... test case. The stimulus components should record events into a file used for initial test case debugging. The ... bench stimulus component mainly has outputs that drive the DUV. The only inputs to these stimulus components will be those ...
... test case. The stimulus components should record events into a file used for initial test case debugging. The ... bench stimulus component mainly has outputs that drive the DUV. The only inputs to these stimulus components will be those ...
77. lappuse
... component of the initiator. As an example, this chapter builds on the cache design shown in Chapter 2 (see Figure 2.20). Figure 3.3 shows that the protocol component ... Test Bench 77.
... component of the initiator. As an example, this chapter builds on the cache design shown in Chapter 2 (see Figure 2.20). Figure 3.3 shows that the protocol component ... Test Bench 77.
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench test bench components tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL