Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
|
No grāmatas satura
1.–5. rezultāts no 80.
xiv. lappuse
... Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.1.5 Design Under Verification . . . . . . . . . . . . . . . . . . . 85 3.2 Observation Points: Black-Box, White-Box and Grey-Box Verification ...
... Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.1.5 Design Under Verification . . . . . . . . . . . . . . . . . . . 85 3.2 Observation Points: Black-Box, White-Box and Grey-Box Verification ...
73. lappuse
... scoreboard components (some environments may not include a scoreboard). Figure 3.1 shows a diagram of a basic verification environment. This environment is referred to as a test bench. In general, a test bench is all the code used to ...
... scoreboard components (some environments may not include a scoreboard). Figure 3.1 shows a diagram of a basic verification environment. This environment is referred to as a test bench. In general, a test bench is all the code used to ...
74. lappuse
... Scoreboard Basic verification environment: a test bench. (Some environments do not include a scoreboard.) (“deterministic”) input sequence to the design. This pre-determined input sequence may be generated in a direct approach or by a ...
... Scoreboard Basic verification environment: a test bench. (Some environments do not include a scoreboard.) (“deterministic”) input sequence to the design. This pre-determined input sequence may be generated in a direct approach or by a ...
78. lappuse
... scoreboard component of the verification environment (described later in this section) participates in this feedback. In the simplest terms, a scoreboard is a temporary holding location for information that the checker will require ...
... scoreboard component of the verification environment (described later in this section) participates in this feedback. In the simplest terms, a scoreboard is a temporary holding location for information that the checker will require ...
80. lappuse
... scoreboard updates s Internals of the DUV for events of interest to the environment At a minimum, the monitor must observe the outputs of the DUV. If the DUV does not adhere to the protocol, then the monitor must return an error. The ...
... scoreboard updates s Internals of the DUV for events of interest to the environment At a minimum, the monitor must observe the outputs of the DUV. If the DUV does not adhere to the protocol, then the monitor must return an error. The ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL