Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 78.
xvi. lappuse
... . . . . . . . . . . . . . 301 7.2.7 Making Rare Events Occur . . . . . . . . . . . . . . . . . . 303 7.2.8 Stimulus Generation of Deadlocks and Livelocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 7.3 Summary ...
... . . . . . . . . . . . . . 301 7.2.7 Making Rare Events Occur . . . . . . . . . . . . . . . . . . 303 7.2.8 Stimulus Generation of Deadlocks and Livelocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 7.3 Summary ...
14. lappuse
... occur in the design. A top-notch verification engineer is invaluable to the design team, combining experience on how to uncover design flaws with the ability to develop tests and checks that guarantee the success of the fabricated chip ...
... occur in the design. A top-notch verification engineer is invaluable to the design team, combining experience on how to uncover design flaws with the ability to develop tests and checks that guarantee the success of the fabricated chip ...
19. lappuse
... occur and that the checking is complete. This requires proficiency in multiple verification techniques, all of which rely on the verification engineer's knack for sniffing out bugs in the design. 1.4 COST OF VERIFICATION Functional ...
... occur and that the checking is complete. This requires proficiency in multiple verification techniques, all of which rely on the verification engineer's knack for sniffing out bugs in the design. 1.4 COST OF VERIFICATION Functional ...
30. lappuse
... occurs, the redundancy path breaks, leading to a verification effort that simply proves that the HDL design is equal to ... occur on very difficult or esoteric problems, there is no shame in discussing the holes in the verification ...
... occurs, the redundancy path breaks, leading to a verification effort that simply proves that the HDL design is equal to ... occur on very difficult or esoteric problems, there is no shame in discussing the holes in the verification ...
43. lappuse
... occur, the verification engineer will not discover the bug in simulation. Controllability and the verification level ... occurs. This makes it difficult to fill the buffer. Figure 2.4 depicts these two cases: in Figure 2.4a, the ...
... occur, the verification engineer will not discover the bug in simulation. Controllability and the verification level ... occurs. This makes it difficult to fill the buffer. Figure 2.4 depicts these two cases: in Figure 2.4a, the ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL