Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 88.
xv. lappuse
... Levels . . . . . . . . . . . . . . . . . . . . . . 143 5.1.2 Verification Aspects of HDLs . . . . . . . . . . . . . . . . . 153 5.2 Simulation Engines: Introduction ... Level Verification Languages . . . Contents xv.
... Levels . . . . . . . . . . . . . . . . . . . . . . 143 5.1.2 Verification Aspects of HDLs . . . . . . . . . . . . . . . . . 153 5.2 Simulation Engines: Introduction ... Level Verification Languages . . . Contents xv.
xvi. lappuse
... Level Verification Languages . . . . . . . . . . . . . 230 6.1.4 Other Test Bench Tools . . . . . . . . . . . . . . . . . . . . . 241 Verification Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 6.2.1 Overview ...
... Level Verification Languages . . . . . . . . . . . . . 230 6.1.4 Other Test Bench Tools . . . . . . . . . . . . . . . . . . . . . 241 Verification Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 6.2.1 Overview ...
16. lappuse
... level chip design Manufacturing HDL implementation (logic design) at RTL level Functional verification Fixes to HDL Tim in g a n a ly s is Physical circuit design via synthesis or custom layout Design sent to fab Fabricated chip System ...
... level chip design Manufacturing HDL implementation (logic design) at RTL level Functional verification Fixes to HDL Tim in g a n a ly s is Physical circuit design via synthesis or custom layout Design sent to fab Fabricated chip System ...
18. lappuse
... Verification requires detailed knowledge of the design that is being verified (the design under verification, or DUV). Understanding of the design comes at two levels: the specification level and the implementation level. The ...
... Verification requires detailed knowledge of the design that is being verified (the design under verification, or DUV). Understanding of the design comes at two levels: the specification level and the implementation level. The ...
22. lappuse
... level verification languages that assist the verification engineer in writing complex simulation environments s Test case generation software that can create multiple simulation test cases based on abstract templates s Simulation farm ...
... level verification languages that assist the verification engineer in writing complex simulation environments s Test case generation software that can create multiple simulation test cases based on abstract templates s Simulation farm ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL