Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 70.
vi. lappuse
... initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval ...
... initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval ...
21. lappuse
... initial line of defense against bugs. Designers should perform a suite of verification tests that ensures a level of quality before delivering HDL to the verification team. No designer wants to “throw HDL over the wall” to the ...
... initial line of defense against bugs. Designers should perform a suite of verification tests that ensures a level of quality before delivering HDL to the verification team. No designer wants to “throw HDL over the wall” to the ...
29. lappuse
... initial tape-out into revised HDL code, which will also contain fixes for any problems found during the hardware debug of the systems test. 1.6.7. Debug. Fabricated. Hardware. (Systems. Test). The design team receives the hardware once the ...
... initial tape-out into revised HDL code, which will also contain fixes for any problems found during the hardware debug of the systems test. 1.6.7. Debug. Fabricated. Hardware. (Systems. Test). The design team receives the hardware once the ...
33. lappuse
... ) Focus on multiple events at the same time (i) Move on to the next product after the initial tape-out because the work is complete VERIFICATION FLOW The verification team spends the majority of their 1.8 Exercises 33.
... ) Focus on multiple events at the same time (i) Move on to the next product after the initial tape-out because the work is complete VERIFICATION FLOW The verification team spends the majority of their 1.8 Exercises 33.
39. lappuse
... initial use. Thus, the bounds in which the verification team works on a core are less defined and put a bigger burden on the team to verify the core in a more aggressive manner, as they must dream of “weird” scenarios. When the core ...
... initial use. Thus, the bounds in which the verification team works on a core are less defined and put a bigger burden on the team to verify the core in a more aggressive manner, as they must dream of “weird” scenarios. When the core ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example execution Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet parameters performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL