Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.–5. rezultāts no 84.
x. lappuse
... driving it up.” Coverage analysis often results in surprises—complex designs, by their very nature, are difficult to grasp, and our intuition is a poor guide to the interactions that are occurring as we simulate the design. Coverage ...
... driving it up.” Coverage analysis often results in surprises—complex designs, by their very nature, are difficult to grasp, and our intuition is a poor guide to the interactions that are occurring as we simulate the design. Coverage ...
6. lappuse
... drive the general specification and architecture. The chip components then take shapae during the high-level design stage, followed by the register transfer level (RTL) implementation in a hardware description language (HDL; usually ...
... drive the general specification and architecture. The chip components then take shapae during the high-level design stage, followed by the register transfer level (RTL) implementation in a hardware description language (HDL; usually ...
14. lappuse
... Drive the state transitions and input scenarios 2. Flag any incorrect behavior exhibited by the design Verification engineers attack the challenge by using two fundamental methods: (1) simulation-based verification and (2) formal ...
... Drive the state transitions and input scenarios 2. Flag any incorrect behavior exhibited by the design Verification engineers attack the challenge by using two fundamental methods: (1) simulation-based verification and (2) formal ...
16. lappuse
... drive development expenses to an unacceptable level and negatively affect the product schedule. A solid verification effort reduces the number of re-spins and removes latent problems, which, if not discovered by verification and a ...
... drive development expenses to an unacceptable level and negatively affect the product schedule. A solid verification effort reduces the number of re-spins and removes latent problems, which, if not discovered by verification and a ...
17. lappuse
... drive early problem discovery Systems test Verification N u m b e r o f bug s Time s FIGURE 1.8 Increasing verification productivity reduces schedule and costs. The figure shows three possible “bug curves.” The longest one stretches ...
... drive early problem discovery Systems test Verification N u m b e r o f bug s Time s FIGURE 1.8 Increasing verification productivity reduces schedule and costs. The figure shows three possible “bug curves.” The longest one stretches ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench test bench components tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL