Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.5. rezultāts no 84.
xiv. lappuse
... Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.1.4 Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.1.5 Design Under Verification . . . . . . . . . . . . . . . . . . . 85 3.2 ...
... Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.1.4 Scoreboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.1.5 Design Under Verification . . . . . . . . . . . . . . . . . . . 85 3.2 ...
45. lappuse
... checker flags an illegal state. One is inadequate without the other. Driving all possible combinations of inputs cannot uncover a bug if the checkers fail to identify the bad condition. Likewise, checking for all possible failures is ...
... checker flags an illegal state. One is inadequate without the other. Driving all possible combinations of inputs cannot uncover a bug if the checkers fail to identify the bad condition. Likewise, checking for all possible failures is ...
50. lappuse
... checker's job to ensure that the DUV behaves correctly based on the stimulus. A DUV behaves correctly when it abides by the design specification and intended function. There are four main sources of checkers. The design and architecture ...
... checker's job to ensure that the DUV behaves correctly based on the stimulus. A DUV behaves correctly when it abides by the design specification and intended function. There are four main sources of checkers. The design and architecture ...
51. lappuse
... checkers for output signals based on the inputs and an understanding of the DUV function. ments on latch counts and physical timing. Further simplifying the verification code is that the environment, unlike the HDL, does not have to ...
... checkers for output signals based on the inputs and an understanding of the DUV function. ments on latch counts and physical timing. Further simplifying the verification code is that the environment, unlike the HDL, does not have to ...
52. lappuse
... checkers from an understanding of the function, properties, and context of the larger design. In this figure, functions of the higher level of hierarchy imply checking on the individual outputs of HDL A and HDL B. The execution unit's ...
... checkers from an understanding of the function, properties, and context of the larger design. In this figure, functions of the higher level of hierarchy imply checking on the individual outputs of HDL A and HDL B. The execution unit's ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench test bench components tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL