Comprehensive Functional Verification: The Complete Industry CycleElsevier, 2005. gada 26. maijs - 704 lappuses One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
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No grāmatas satura
1.5. rezultāts no 45.
9. lappuse
... arrays (RAM), and combinatorial logic, all of which control the behavior of the chip. The chip inputs manipulate the internal logic, causing it to act on the applied stimulus. Main_Street reset timer_pulse Elm_Street reg_ proc latch clk ...
... arrays (RAM), and combinatorial logic, all of which control the behavior of the chip. The chip inputs manipulate the internal logic, causing it to act on the applied stimulus. Main_Street reset timer_pulse Elm_Street reg_ proc latch clk ...
10. lappuse
... arrays, into the next and future states of the chip. At a given point in time, a chip can be in any one of an enormous number of possible current states.1 Furthermore, the next state of the chip, determined by the current state and the ...
... arrays, into the next and future states of the chip. At a given point in time, a chip can be in any one of an enormous number of possible current states.1 Furthermore, the next state of the chip, determined by the current state and the ...
12. lappuse
... array space and a number of internal states produces too many possible combinations to verify exhaustively. To ... arrays, and hundreds of input pins. Rather than verify the entire chip at once, the verification team will carve out ...
... array space and a number of internal states produces too many possible combinations to verify exhaustively. To ... arrays, and hundreds of input pins. Rather than verify the entire chip at once, the verification team will carve out ...
13. lappuse
... array space How do we know if a pixel is wrong? Does the video appear correctly on a monitor? Streaming-encoded video In the traffic signal example, a verification engineer will expect certain behavior from the design. Stimulus is ...
... array space How do we know if a pixel is wrong? Does the video appear correctly on a monitor? Streaming-encoded video In the traffic signal example, a verification engineer will expect certain behavior from the design. Stimulus is ...
21. lappuse
... array sizes, and state machine transitions. This information guides the verification team in creating complete test plans and executing their work. Design management teams often calculate the engineering cost of verification by the ...
... array sizes, and state machine transitions. This information guides the verification team in creating complete test plans and executing their work. Design management teams often calculate the engineering cost of verification by the ...
Saturs
3 | |
SIMULATIONBASED VERIFICATION | 139 |
FORMAL VERIFICATION | 437 |
COMPREHENSIVE VERIFICATION | 537 |
CASE STUDIES | 601 |
VERIFICATION GLOSSARY | 641 |
REFERENCES | 657 |
SUBJECT INDEX | 663 |
Citi izdevumi - Skatīt visu
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John Goss,Wolfgang Roesner Ierobežota priekšskatīšana - 2005 |
Comprehensive Functional Verification: The Complete Industry Cycle Bruce Wile,John C. Goss,Wolfgang Roesner Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
abstraction algorithm array assertions behavior blocks Boolean cache Calc1 Calc2 cation Chapter checker checking components chip clock command complete constraints create debug design team design under verification drive error escape analysis event-driven example Figure formal verification functional verification FV tools hardware hardware description language ification implementation initial input instruction stream interface language latches level of verification logic memory microprocessor monitor multiple occur on-the-fly opcode OpenVera operand operation output packet performance pipeline port problem processor property specification language protocol queue random re-use reference model regression requires reset scan ring scenarios scoreboard sequence signal simulation engine specification stimulus component structure tape-out test bench test bench components tion transaction unit update valid verifica verification components verification cycle verification engineer verification environment verification plan verification team Verilog VHDL