Proceedings of the 1995 International Conference on Parallel Processing: August 14 - 18, 1995, 3. sējumsCRC Press, 1995. gada 8. aug. - 256 lappuses This set of technical books contains all the information presented at the 1995 International Conference on Parallel Processing. This conference, held August 14 - 18, featured over 100 lectures from more than 300 contributors, and included three panel sessions and three keynote addresses. The international authorship includes experts from around the globe, from Texas to Tokyo, from Leiden to London. Compiled by faculty at the University of Illinois and sponsored by Penn State University, these Proceedings are a comprehensive look at all that's new in the field of parallel processing. |
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xiii. lappuse
... Scheme on 2 - D Mesh Parallel Computers III - 9 T - Y . Lee , C. S. Raghavendra , and J. B. Nicholas ( C ) : Antipodality - Based Time - Optimal Computation on Meshes with Multiple Broadcasting III - 17 V. Bokka , H. Gurla , S. Olariu ...
... Scheme on 2 - D Mesh Parallel Computers III - 9 T - Y . Lee , C. S. Raghavendra , and J. B. Nicholas ( C ) : Antipodality - Based Time - Optimal Computation on Meshes with Multiple Broadcasting III - 17 V. Bokka , H. Gurla , S. Olariu ...
xiv. lappuse
... Schemes G. Karypis and V. Kumar Session 6C : Algorithms on Networks - I Chair : N. Ranganathan , University of South Florida ( R ) : Optimal Circuit - Switched Routing in Hypercubes A. Mahmood , D. J. Lynch , and R. B. Shaffer ( C ) ...
... Schemes G. Karypis and V. Kumar Session 6C : Algorithms on Networks - I Chair : N. Ranganathan , University of South Florida ( R ) : Optimal Circuit - Switched Routing in Hypercubes A. Mahmood , D. J. Lynch , and R. B. Shaffer ( C ) ...
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Saturs
Control Applications | 76 |
Graph Algorithms | 97 |
Algorithms on Networks I | 123 |
Nonnumerical Algorithms | 151 |
Algorithms on Networks II | 176 |
Partitioning and Scheduling | 203 |
Preface iii | |
Bieži izmantoti vārdi un frāzes
alignment architecture array ASDEX Upgrade biconnected component binary block block-row blocksize bounding box broadcast cessor column communication connected convolution corresponding cycle defined disk distributed DMBC ear decomposition edge-cut elements exchange execution factorization Fibonacci Fibonacci tree FPGAs gorithm graph graph partitioning grid Gröbner basis Hamming distance hypercube IEEE implementation input instantiations Intel Paragon iteration label lagged Fibonacci Lemma linear load balancing matrix memory method multicomputer multilevel multiple multiprocessor neighbors node number of processors obtained operations optimal output pair parallel algorithms parallel computers Parallel Processing partition path PEC(i performance phase pixel polygons polynomials problem Proc R-tree reconfigurable mesh rithm routing algorithm rule safety level scalable scheme sequence sequential SIMD simulation sorting sparse sparse matrix speedup split step strategy switching techniques Theorem tion tokamak transputer tree unicasting values vector vertex vertices workload