Speculative Execution in High Performance Computer ArchitecturesDavid Kaeli, Pen-Chung Yew CRC Press, 2005. gada 26. maijs - 456 lappuses Until now, there were few textbooks that focused on the dynamic subject of speculative execution, a topic that is crucial to the development of high performance computer architectures. Speculative Execution in High Performance Computer Architectures describes many recent advances in speculative execution techniques. It covers cutting-edge research |
Saturs
1 | |
9 | |
29 | |
Trace Caches | 87 |
Branch Predication | 109 |
Multipath Execution | 135 |
Data Cache Prefetching | 161 |
Address Prediction | 187 |
Instruction Precomputation | 245 |
ProfileBased Speculation | 269 |
Compilation and Speculation | 301 |
Multithreading and Speculation | 333 |
Exploiting LoadStore Parallelism via Memory Dependence Prediction | 355 |
Resource Flow Microarchitectures | 393 |
Index | 421 |
Data Speculation | 215 |
Citi izdevumi - Skatīt visu
Speculative Execution in High Performance Computer Architectures David Kaeli,Pen-Chung Yew Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
accuracy additional allows analysis Annual applications approach Architecture array assigned basic bits block branch prediction called compiler Computer Computer Architecture conditional Conference correct cycle data dependence dependence speculation determine discussed dynamic effective entry example execution fetch Figure Filed flow frequency function hardware identify implementation improve increase input instruction cache International Symposium issue latency limited load loop machine mechanism memory dependence memory disambiguation Microarchitecture misspeculation multipath multiple operand operations optimizations parallelism path performance pipeline pointer possible potential precomputation predictor prefetching present Proceedings processor proposed recovery reduce redundant reference requires result scheduling scheme sequence shown shows single speculation static stream buffer stride structures taken techniques thread tion trace cache tree types unique unit update value prediction
Populāri fragmenti
73. lappuse - ... future of wires. In Semiconductor Research Corporation Workshop on Interconnects for Systems on a Chip, May 1999. [12] MS Hrishikesh, Norman P. Jouppi, Keith I. Farkas, Doug Burger, Stephen W. Keckler, and Premkishore Shivakumar. The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 14-24, May 2002. [13] J. Huh, D. Burger, and SW Keckler. Exploring the design space of future CMPs. In...
27. lappuse - Keckler, and D. Burger. Clock rate versus IPC: The end of the road for conventional microarchitectures.
182. lappuse - C. Ding and K. Kennedy. Improving cache performance in dynamic applications through data and computation reorganization at run time. In Proceedings of the SIGPLAN '99 Conference on Programming Language Design and Implementation, Atlanta, GA, May 1999.
183. lappuse - In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pages 40-46, October 1999.
184. lappuse - In Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 1 15-126, San Jose, California, October 1998. ACM. [13] C.-L. Yang and A. Lebeck. Push vs. pull: Data movement for linked data structures.
131. lappuse - Hwu. Integrated predicated and speculative execution in the impact epic architecture.
181. lappuse - WY Chen, SA Mahlke, PP Chang, and WW Hwu. Data access microarchitectures for superscalar processors with compiler-assisted data prefetching.
75. lappuse - December 1997. pp. 358-68. [6] E. Jacobsen, E. Rotenberg, and JE Smith. Assigning confidence to conditional branch predictions.