 | Alan Gatherer, Edgar Auslander - 2001 - 430 lapas
...Papers. 1996. pp. 14-15. [14] Shigematsu, S.. Mutoh, S.. Matsuya. Y.. Tanabe, Y. and Yamada. J.. 'A IV High-Speed MTCMOS Circuit Scheme for Power-Down Application...IEEE Journal of Solid-State Circuits, Vol. 32, No. 6, 1997. pp. 861-869. 1 15] Kumagai. K.. Iwaki. H.. Yoshida. H.. Suzuki. H.. Yamada. T. and Kurosawa,... | |
 | Mohab Anis, Mohamed I. Elmasry - 2003 - 248 lapas
...the IEEE Custom Integrated Circuits Conference, 1996, pp. 1 1 1-1 14. [56] S. Shigematsu, S. Mutah, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V High-Speed...IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 861-869, 1997. [57] M. Stan, "CMOS Circuits with Subvolt Supply Voltages," IEEE Design & Test of... | |
 | Mohab Anis, Mohamed I. Elmasry - 2003 - 248 lapas
...Journal of Solid-State Circuits, vol. 31, no. 1 1, pp. 1795-1802, 1996. [2] S. Shigematsu, S. Mutah, Y. Matsuya, Y. Tanabe, and J. Yamada, "A 1-V High-Speed...Power-Down Application Circuits," IEEE Journal of Solid-Slate Circuits, vol. 32, no. 6, pp. 861-869, 1997. [3] H. Akamatsu, T. Iwata, H. Yamamoto, T.... | |
 | P. van der Meer, A. van Staveren, Arthur H.M. van Roermund - 2004 - 176 lapas
...vlsi cmos circuits: Smart series switch. In Proceedings of the ESSCIRC. IEEE, September 2002. [70] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and...application circuits. IEEE Journal of Solid-State Circuits, 32(6):861 - 869, June 1997. [72] Y. Oowaki, M. Noguchi, S. Takagi, D. Takashima, M. Ono, Y. Matsunaga,... | |
 | Christian Piguet - 2018 - 912 lapas
...for dual supply systems, Proc. Int. Symp. on Low-Power Electron. and Design, 2003, pp. 164-167. [21] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, A 1 -V high-speed MTCMOS circuit scheme for power-down application circuits, IEEE J. Solid-State Circuits,... | |
 | David Chinnery, Kurt Keutzer - 2008 - 388 lapas
...Computer-Aided Design, 2002, pp. 721-725. [4] Shigematsu, S., Mutoh, S., Matsuya, Y., Tanabe, Y. and Yamada, J., "A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down...of Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 861-869. [5] Shigematsu, S., Mutoh, S., Matsuya, Y. and Yamada, J., "A 1-V High-Speed MTCMOS Circuit... | |
| |
S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, A 1-V high-speed MTCMOS circuit scheme for power-down application circuits, IEEE J. 