Leakage in Nanometer CMOS TechnologiesSiva G. Narendra, Anantha P. Chandrakasan Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. |
No grāmatas satura
1.–5. rezultāts no 65.
vi. lappuse
... Schemes 7.5 Gate-Source Reverse Biasing Schemes 7.6 Applications to RAM Cells 7.7 Applications to Peripheral Circuits 7.8 Future Prospects 7.9 Conclusion References 163 164 168 171 175 180 186 195 196 196 LAWRENCE CLARK 11.1 ...
... Schemes 7.5 Gate-Source Reverse Biasing Schemes 7.6 Applications to RAM Cells 7.7 Applications to Peripheral Circuits 7.8 Future Prospects 7.9 Conclusion References 163 164 168 171 175 180 186 195 196 196 LAWRENCE CLARK 11.1 ...
17. lappuse
... scheme to solve all sources of leakage and its impact, and given that these solutions could transcend across the ... schemes that while occupying silicon area enable integration of additional transistors for computation. All of this will ...
... scheme to solve all sources of leakage and its impact, and given that these solutions could transcend across the ... schemes that while occupying silicon area enable integration of additional transistors for computation. All of this will ...
18. lappuse
... Scheme,” IEEE J Solid-State Circuits, vol. 31, pp. 1770-1779, Nov. 1996. X. Huang, W-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor, C. Hu, "Sub ...
... Scheme,” IEEE J Solid-State Circuits, vol. 31, pp. 1770-1779, Nov. 1996. X. Huang, W-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y-K. Choi, K. Asano, V. Subramanian, T-J. King, J. Bokor, C. Hu, "Sub ...
22. lappuse
... scheme which exploits the large reduction in leakage current achievable by simultaneously turning OFF more than one transistor in NMOS or PMOS stacks. Usually, a large circuit block consists of a significant number of logic gates where ...
... scheme which exploits the large reduction in leakage current achievable by simultaneously turning OFF more than one transistor in NMOS or PMOS stacks. Usually, a large circuit block consists of a significant number of logic gates where ...
30. lappuse
... scheme offers leakage reduction with minimal overheads in area, power, and process technology change. In particular, this technique has the potential to replace the need for a high-Vi transistor for standby leakage. Extensive results ...
... scheme offers leakage reduction with minimal overheads in area, power, and process technology change. In particular, this technique has the potential to replace the need for a high-Vi transistor for standby leakage. Extensive results ...
Saturs
Chapter 6 | 141 |
Chapter 7 | 163 |
Chapter 8 | 200 |
L | 209 |
Chapter 9 | 211 |
Chapter 10 | 234 |
VVV0xW+2+ 20 1 | 236 |
Periphery | 254 |
Chapter 4 | 77 |
11 | 81 |
Vdd I t I | 96 |
botas bbarabosse cseldk14keyb long sandsly | 102 |
Chapter 5 | 105 |
6 | 108 |
aget | 121 |
Chapter 11 | 257 |
i | 269 |
i | 274 |
Chapter 12 | 281 |
B | 291 |
Figure 129 Carbon nanotube structures | 298 |
Citi izdevumi - Skatīt visu
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2005 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
achieved active mode adaptive additional allows applied approach becomes biasing block body bias capacitance cause cell channel length Chapter charge chip circuit clock CMOS compared critical defective delay depends described devices drain drive dynamic effect energy example Figure frequency higher IDDQ IEEE impact implementation improve increase input junction larger leakage current leakage power leakage reduction limit logic lower measured microprocessor minimize MOSFET MTCMOS needed NMOS node noise operation output oxide parameter path penalty performance PMOS power gating power supply power switch presented reduce leakage reduced savings scaling scheme selected shown in Figure shows signal sleep transistor smaller solution speed SRAM stack standby mode sub-threshold leakage substrate supply voltage techniques temperature threshold voltage tunneling turned variation virtual width
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Atsauces uz šo grāmatu
Low Power Methodology Manual: For System-on-Chip Design David Flynn,Rob Aitken,Alan Gibbons,Kaijian Shi Ierobežota priekšskatīšana - 2007 |
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |