Leakage in Nanometer CMOS TechnologiesSiva G. Narendra, Anantha P. Chandrakasan Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. |
No grāmatas satura
1.–5. rezultāts no 45.
7. lappuse
... high permittivity gate dielectric, metal gate, novel transistor structures and circuit based techniques [12, 13, 14, 15, 16, 17]. The use of high ... VT to maintain 1. Taxonomy of Leakage 7.
... high permittivity gate dielectric, metal gate, novel transistor structures and circuit based techniques [12, 13, 14, 15, 16, 17]. The use of high ... VT to maintain 1. Taxonomy of Leakage 7.
18. lappuse
... High Performance,” Intl. Symp. Low Power Electronics and Design, pp. 163-168 ... high-K gate dielectrics on deep submicrometer CMOS transistor and circuit ... (VT) Scheme,” IEEE J Solid-State Circuits, vol. 31, pp. 1770-1779, Nov. 1996 ...
... High Performance,” Intl. Symp. Low Power Electronics and Design, pp. 163-168 ... high-K gate dielectrics on deep submicrometer CMOS transistor and circuit ... (VT) Scheme,” IEEE J Solid-State Circuits, vol. 31, pp. 1770-1779, Nov. 1996 ...
22. lappuse
... high-Vi transistor in a dual-Vt design. In a dual-Vt design the low-V, transistors are used in performance critical paths and the high-V. transistors in the rest. Further details of dual-V, design technique will be described in Chapter ...
... high-Vi transistor in a dual-Vt design. In a dual-Vt design the low-V, transistors are used in performance critical paths and the high-V. transistors in the rest. Further details of dual-V, design technique will be described in Chapter ...
30. lappuse
... high-Vt. Figure 2-8. 2 NMOS stack in a NAND gate and DC solution for intermediate node voltage. A 2-input NAND gate is used to illustrate the dynamics of leakage reduction in 2-transistor stacks with both transistors OFF, as shown in ...
... high-Vt. Figure 2-8. 2 NMOS stack in a NAND gate and DC solution for intermediate node voltage. A 2-input NAND gate is used to illustrate the dynamics of leakage reduction in 2-transistor stacks with both transistors OFF, as shown in ...
31. lappuse
... High Vt 50 70 90 110 Temperature 3 0 Figure 2-9. Leakage reduction in 2 NMOS and 2 PMOS stacks at different temperatures and different target threshold voltages, from simulations. High Vt Low Vt 2 NMOS 10.7X 9.96X 3 NMOS 21.1X 18.8X 4 ...
... High Vt 50 70 90 110 Temperature 3 0 Figure 2-9. Leakage reduction in 2 NMOS and 2 PMOS stacks at different temperatures and different target threshold voltages, from simulations. High Vt Low Vt 2 NMOS 10.7X 9.96X 3 NMOS 21.1X 18.8X 4 ...
Saturs
Chapter 6 | 141 |
Chapter 7 | 163 |
Chapter 8 | 200 |
L | 209 |
Chapter 9 | 211 |
Chapter 10 | 234 |
VVV0xW+2+ 20 1 | 236 |
Periphery | 254 |
Chapter 4 | 77 |
11 | 81 |
Vdd I t I | 96 |
botas bbarabosse cseldk14keyb long sandsly | 102 |
Chapter 5 | 105 |
6 | 108 |
aget | 121 |
Chapter 11 | 257 |
i | 269 |
i | 274 |
Chapter 12 | 281 |
B | 291 |
Figure 129 Carbon nanotube structures | 298 |
Citi izdevumi - Skatīt visu
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2005 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
achieved active mode adaptive additional allows applied approach becomes biasing block body bias capacitance cause cell channel length Chapter charge chip circuit clock CMOS compared critical defective delay depends described devices drain drive dynamic effect energy example Figure frequency higher IDDQ IEEE impact implementation improve increase input junction larger leakage current leakage power leakage reduction limit logic lower measured microprocessor minimize MOSFET MTCMOS needed NMOS node noise operation output oxide parameter path penalty performance PMOS power gating power supply power switch presented reduce leakage reduced savings scaling scheme selected shown in Figure shows signal sleep transistor smaller solution speed SRAM stack standby mode sub-threshold leakage substrate supply voltage techniques temperature threshold voltage tunneling turned variation virtual width
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Atsauces uz šo grāmatu
Low Power Methodology Manual: For System-on-Chip Design David Flynn,Rob Aitken,Alan Gibbons,Kaijian Shi Ierobežota priekšskatīšana - 2007 |
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |