Advances in Computer Systems Architecture: 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings

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Springer Science & Business Media, 2005. gada 13. okt. - 833 lappuses
On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year’s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.
 

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Atlasītās lappuses

Saturs

Processor Architecture for Trustworthy Computers
1
Efficient Voltage Scheduling and EnergyAware Cosynthesis for RealTime Embedded Systems
3
EnergyEffective Instruction Fetch Unit for Wide Issue Processors
15
RuleBased PowerBalanced VLIW Instruction Scheduling with Uncertainty
28
An Innovative Instruction Cache for Embedded Processors
41
Dynamic Voltage Scaling for Power Aware Fast Fourier Transform FFT Processor
52
Design of an Efficient MultiplierLess Architecture for Multidimensional Convolution
65
A Pipelined Hardware Architecture for Motion Estimation of H264AVC
79
Morphable Structures for Reconfigurable Instruction Set Processors
450
Implementation of a Hybrid TCPIP Offload Engine Prototype
464
A New Interconnection Network Based on Matrix Operations
478
The Channel Assignment Algorithm on RPk Networks
488
Extending Address Space of IP Networks with Hierarchical Addressing
499
An Attractive Alternative to the Pyramid
509
Building a Terabit Router with XD Networks
520
A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time
529

Embedded Intelligent Imaging OnBoard Small Satellites
90
Architectural Enhancements for Color Image and Video Processing on Embedded Systems
104
A Portable Doppler Device Based on a DSP with High Performance Spectral Estimation and Output
118
A PowerEfficient Processor Core for Reactive Embedded Applications
131
A Stream Architecture Supporting Multiple Stream Execution Models
143
The Challenges of Massive OnChip Concurrency
157
Design of FineGrain Multicontext Reconfigurable Processing Unit
171
Modularized Redundant Parallel Virtual File System
186
ResourceDriven Optimizations for TransientFault Detecting SuperScalar Microarchitectures
200
A FaultTolerant Routing Strategy for FibonacciClass Cubes
215
Embedding of Cycles in the Faulty Hypercube
229
Improving the Performance of GCC by Exploiting IA64 Architectural Features
236
An Integrated Partitioning and Scheduling Based Branch Decoupling
252
A Register Allocation Framework for Banked Register Files with Access Constraints
269
Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems
281
Irregular Redistribution Scheduling by Partitioning Messages
295
Making PowerEfficient Data Value Predictions
310
Speculative Issue Logic
323
Using Decision Trees to Improve ProgramBased and ProfileBased Static Branch Prediction
336
Arithmetic Data Value Speculation
353
Exploiting ThreadLevel Speculative Parallelism with Software Value Prediction
367
Challenges and Opportunities on Multicore Microprocessor
389
SoftwareOriented SystemLevel Simulation for Design Space Exploration of Reconfigurable Architectures
391
A Switch Wrapper Design for SNA OnChipNetwork
405
A Configuration System Architecture Supporting BitStream Compression for FPGAs
415
Biological Sequence Analysis with Hidden Markov Models on an FPGA
429
FPGAs for Improved Energy Efficiency in Processor Based Systems
440
A Direct3DBased LargeScale Display Parallel Rendering System Architecture for Clusters
540
Determining Optimal Grain Size for Efficient Vector Processing on SIMD Image Processing Architectures
551
A Technique to Reduce Preemption Overhead in RealTime Multiprocessor Task Scheduling
566
Minimizing Power in HardwareSoftware Partitioning
580
Exploring Design Space Using Transaction Level Models
589
Increasing Embedding Probabilities of RPRPs in RIN Based BIST
600
A Practical Test Scheduling Using NetworkBased TAM in Network on Chip Architecture
614
DRIL A Flexible Architecture for Blowfish Encryption Using Dynamic Reconfiguration Replication InnerLoop Pipelining Loop Folding Techniques
625
Efficient Architectural Support for Secure BusBased Shared Memory Multiprocessor
640
Covert Channel Analysis of the PasswordCapability System
655
Comparing LowLevel Behavior of SPEC CPU and Java Workloads
669
Application of RealTime ObjectOriented Modeling Technique for RealTime Computer Control
680
VLSI Performance Evaluation and Analysis of Systolic and Semisystolic Finite Field Multipliers
693
Analysis of RealTime Communication System with Queuing Priority
707
FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile AdHoc Networks
714
A Study on the Performance Evaluation of Forward Link in CDMA Mobile Communication Systems
728
Cache Leakage Management for Multiprogramming Workloads
736
A Memory Bandwidth Effective Cache Store Miss Policy
750
ApplicationSpecific HardwareDriven Prefetching to Improve Data Cache Performance
761
Targeted Data Prefetching
775
AreaTime Efficient Systolic Architecture for the DCT
787
Efficient VLSI Architectures for Convolution and Lifting Based 2D Discrete Wavelet Transform
795
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry LookAhead and Other Adder Architectures
805
Implementation and Analysis of TCPIP Offload Engine and RDMA Transfer Mechanisms on an Embedded System
818
Author Index
831
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